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Semiconductor-based quantum registers require scalable quantum-dots (QDs) to be accurately located in close proximity to and independently addressable by external electrodes. Si-based QD qubits have been realized in various lithographically-defined Si/SiGe heterostructures and validated only for milli-Kelvin temperature operation. QD qubits have recently been explored in germanium (Ge) materials systems that are envisaged to operate at higher temperatures, relax lithographic-fabrication requirements, and scale up to large quantum systems. We report the unique scalability and tunability of Ge spherical-shaped QDs that are controllably located, closely coupled between each another, and self-aligned with control electrodes, using a coordinated combination of lithographic patterning and self-assembled growth. The core experimental design is based on the thermal oxidation of poly-SiGe spacer islands located at each sidewall corner or included-angle location of Si3N4/Si-ridges with specially designed fanout structures. Multiple Ge QDs with good tunability in QD sizes and self-aligned electrodes were controllably achieved. Spherical-shaped Ge QDs are closely coupled to each other via coupling barriers of Si3N4 spacer layers/c-Si that are electrically tunable via self-aligned poly-Si or polycide electrodes. Our ability to place size-tunable spherical Ge QDs at any desired location, therefore, offers a large parameter space within which to design novel quantum electronic devices.

We report the first-of-kind scalability and tunability of Ge QDs that are controllably sized, closely coupled, and self-aligned with control gates, using a combination of lithographic patterning, spacer technology, and self-assembled growth. The core experimental design is based on the thermal oxidation of poly-SiGe spacer islands designated at each included-angle location of designed Si 3 N 4 /c-Si ridge structures. Multiple Ge QDs with good size tunability of 7–20 nm were controllably achieved by adjusting the process times for deposition, etch back and thermal oxidation of poly-SiGe spacer islands. Our Ge QDs array provides a common platform for engineering diverse QD electronic devices with desired reconfigurability and optimizing their performance.

Starting with our remarkable discovery of spherical germanium (Ge) quantum dot (QD) formation, we have embarked on an exciting journey of further discovery, all the while maintaining CMOS-compatible processes. We have taken advantage of the many peculiar and symbiotic interactions of Si, Ge and O interstitials to create a novel portfolio of electronic, photonic and quantum computing devices. This paper summarizes several of these completely new and counter-intuitive accomplishments. Using a coordinated combination of lithographic patterning and self-assembly, size-tunable spherical Ge QDs were controllably placed at designated spatial locations within Si-containing layers. We exploited the exquisite control available through the thermal oxidation of Si 1-x Ge x patterned structures in proximity to Si 3 N 4 /Si layers. Our so-called "designer" Ge QDs have succeeded in opening up myriad device possibilities, including paired QDs for qubits, single-hole transistors (SHTs) for charge sensing, photodetectors and light-emitters for Si photonics, and junctionless (JL) FETs using standard Si processing.

We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO 2 /Si 1-x Ge x channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5–90nm), SiO 2 thickness (2–4nm), and Ge content (x = 0.65–0.85) and strain engineering (e comp = 1–3%) of the Si 1-x Ge x are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. L G of 75nm JL n-FETs feature I ON /I OFF > 5×108, I ON > 500µA/µm at V DS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW–mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300–1600nm (NUV-NIR) are observed on 5–100nm Ge NPs. Our gate stack of Ge NP/SiO 2 /Si 1-x Ge x enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.

We report a novel visible-near infrared photoMOSFET containing a self-organized, gate-stacking heterostructure of SiO2/Ge-dot/SiO2/SiGe-channel on Si substrate that is simultaneously fabricated in a single oxidation step. Our typical photoMOSFETs exhibit very large photoresponsivity of 1000-3000A/W at low optical power (< 0.1μW) or large photocurrent gain of 103-108A/A with a wide dynamic power range of at least 6 orders of magnitude (nW-mW) linearity at 400-1250 nm illumination, depending on whether the photoMOSFET operates at VG = + 3- + 4.5V or -1- + 1V. Numerical simulations reveal that photocarrier confinement within the Ge dots and the SiGe channel modifies the oxide field and the surface potential of SiGe, significantly increasing photocurrent and improving linearity.