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Presilicon modeling is a crucial and integral part of processor microarchitecture definition and optimization. In this article, I attempt to provide a retrospective view of IBM's POWER and PowerPC microprocessors, through the lens of someone who has been associated with such modeling in support of microarchitecture definition and optimization from the earliest days of this particular family of processors. The focus in the early/mid-1980s was on cycle-accurate performance modeling; much later, beginning in 1999 or so, the looming power wall triggered a new era of power-performance modeling at the microarchitecture level. Subsequently, temperature-aware and reliability-aware modeling were added dimensions that CMOS technology evolution drove us into. The problem of model validation is an unavoidable aspect of presilicon modeling. Without that mindset, the microarchitecture definition team can make serious mistakes, which results in unpleasant postsilicon surprises. I provide pointers to early approaches in addressing this issue. The article attempts to mention the contributions of many talented researchers and engineers that have, over the years, contributed immensely to the evolution of the POWER/PowerPC microprocessors from earliest research concepts through the recently announced POWER10—using model-based analysis to ensure competitive performance growth.

It was a different computing world in the late 1980s. Many if not most researchers in the computer architecture area had become convinced that complex instruction sets such as the Intel x86 were doomed in light of the many advantages promised by reduced instruction set architecture publications. There were many voices within Intel urging upper management to abandon x86 and get started on some alternative. Even engineers who had worked on Intel's then-flagship 486 were expressing serious reservations about whether the x86 architecture could be “dragged further up the hill” to be, if not directly competitive with emerging RISC designs, at least close enough for x86 to remain profitable.

Nearly 50 years ago, Intel created the world’s first commercially produced microprocessor—the 4004 (ref. 1), a modest 4-bit CPU (central processing unit) with 2,300 transistors fabricated using 10 μm process technology in silicon and capable only of simple arithmetic calculations. Since this ground-breaking achievement, there has been continuous technological development with increasing sophistication to the stage where state-of-the-art silicon 64-bit microprocessors now have 30 billion transistors (for example, the AWS Graviton2 (ref. 2) microprocessor, fabricated using 7 nm process technology). The microprocessor is now so embedded within our culture that it has become a meta-invention—that is, it is a tool that allows other inventions to be realized, most recently enabling the big data analysis needed for a COVID-19 vaccine to be developed in record time. Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). Separate from the mainstream semiconductor industry, flexible electronics operate within a domain that seamlessly integrates with everyday objects through a combination of ultrathin form factor, conformability, extreme low cost and potential for mass-scale production. PlasticARM pioneers the embedding of billions of low-cost, ultrathin microprocessors into everyday objects. Flexible electronic platforms would enable the integration of functional electronic circuitry with many everyday objects; here, a low-cost and fully flexible 32-bit microprocessor is produced.

Code compression is widely used to reduce the footprint of code memory in cost-sensitive embedded systems. However, despite the small code size, the decompressor and the address translator required to support the code compression incur energy and area overheads. To reduce such overheads while still supporting code compression, we co-architect the instruction cache and decompression system (CID). In CID, each component is placed at the optimal location and the instruction cache is redesigned to recognize the compression state and retain the original address, through the cache division and address space decompression process. As a result of the cache division, the energy consumption and area overheads of the CID instruction cache are reduced. Since the decompressor overhead depends on the code compression technique, we propose a new code compression technique called entropy-based pattern code compression, which reduces overheads of the decompressor. Our experimental results show that the total energy consumption of the instruction cache and decompression system is reduced by up to 29.7 percent and their area is reduced by up to 15.4 percent compared to the post-cache architecture with almost no performance degradation, while achieving an 18.8 percent improvement in the compression ratio compared to the state-of-the-art code compression technique.

Neural network (NN) accelerators based on resistive random access memory (ReRAM) have been widely investigated as a promising solution to address the memory wall challenge, due to its capability of processing-in-memory with extremely high density. However, the performance of these accelerators is bounded by the peripheral circuits and the interconnection. And they also suffer from accuracy issue and flexibility issue caused by the device-variation and the in-situ computation mode respectively. Solving these issues with hardware will further offset the performance. Enlightened by the design principle of conventional reduced instruction set computer (RISC), this article proposes a new software/hardware system for ReRAM-based NN acceleration, which achieves complex functions with sophisticated software tools while making the hardware much more compact and efficient, in order to fully utilize ReRAM potential. The hardware architecture, Field Programmable Synapse Array (FPSA), provides high-density reconfigurable logic, wires, and computational resources based on ReRAM-crossbar. Accordingly, the software can convert various types of NNs, including dynamic NNs, into equivalent networks that meet hardware constraints with negligible accuracy loss and optimize the scheduling and mapping of the latter onto FPSA. Further evaluations show that compared to one state-of-the-art ReRAM-based NN accelerator, PRIME, our approach achieves up to $1000\times$ 1000 × speedup.

This papers deals with base design of the RISC-V 32b processor. It is used to support many additional commands including hardware loops, post-upgrade and save instructions and additional ALU instructions. RISC processors can be used in different ways, depending on speed and power consumption. Organized to design low power RISC processors through design and solution processes. The speed can also be increased by using the correct clock method. Decoding of execution, memory and rewriting. A one-sided clock signal is used for the middle stage. MIPS V adds a new data type, Single Associated (PS), which stores two single-point floating point numbers (32-bit) in a list of 64-bit floating point numbers. Existing floating point statement variants have been added for arithmetic operations, suitability and limitations to work with this type of data using the SIMD method. New instructions for downloading, transferring and transferring PS data have been added. This is the first command to skip the floating point SIMD with the available fonts.

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64-core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-on-chip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs $1.29\times $ power and $2.19\times $ area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs.

Recently, extensive research attention has been drawn to the program executing security of embedded processor since increasing code tamper attacks, as well as transient faults severely affect the safety of embedded systems. The security monitoring and fault recovery technique is one of the effective methods to ensure the security and performance of embedded devices. In this article, an architecture for the security monitoring and fault recovery is proposed for run-time program execution, which builds a Monitoring Cache (M-Cache) and then checks the integrity based on reference data. Especially, the proposed architecture will build the checkpoint once the M-Cache is missed and also take the rollback operation after the unsuccessful of integrity check. In addition, three tampered positions (e.g., instruction register within the pipeline, instruction within the cache, and code within memory) have been elaborately focused on to guarantee the normal running of the embedded system. Eventually, by adopting the open RISC processor for algorithm implementation and verification, the proposal has been proven to be promising for the detection of a fault or tampered program, as well as the fast recovery of running environment and code.

Over the last decade, open source hardware (OSHW) has matured, including a flourishing OSHW community developing projects like RISC -V. The new IEEE Standards Association Open platform enables proficiency and knowledge of OSHW's potential and challenges. A recognized definition of open source hardware (OSHW) is maintained by the Open Source Hardware Association (OSHWA). The wisdom of this definition is that it lists promising as well as challenging features of OSHW. It applies to "tangible artifacts -machines, devices, or other physical things -whose design has been released to the public in such a way that anyone can make, modify, distribute, and use those things."

The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8–12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.

The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.

The article is devoted to the analysis of RISC-processor blocks for fault tolerance, which was carried out on the example of the 1890vm2t processor. the paper describes the block diagram of this processor and the methodology for evaluating the fault tolerance of the multiplication-division module MDUnit. The evaluation of the failure tolerance and the dependences of the values share about the results and formulated requirements to architecture functional blocks.

Analog compute-in-memory with resistive random access memory (RRAM) devices promises to overcome the data movement bottleneck in data-intensive artificial intelligence (AI) and machine learning. RRAM crossbar arrays improve the efficiency of vector-matrix multiplications (VMMs), which is a vital operation in these applications. The prototype IC is the first complete, fully integrated analog-RRAM CMOS coprocessor. This article focuses on the digital and analog circuitry that supports efficient and flexible RRAM-based computation. A passive $54\times108$ RRAM crossbar array performs VMM in the analog domain. Specialized mixed-signal circuits stimulate and read the outputs of the RRAM crossbar. The single-chip CMOS prototype includes a reduced instruction set computer (RISC) processor interfaced to a memory-mapped mixed-signal core. In the mixed-signal core, ADCs and DACs interface with the passive RRAM crossbar. The RISC processor controls the mixed-signal circuits and the algorithm data path. The system is fully programmable and supports forward and backward propagation. As proof of concept, a fully integrated 0.18- $\mu \text{m}$ CMOS prototype with a postprocessed RRAM array demonstrates several key functions of machine learning, including online learning. The mixed-signal core consumes 64 mW at an operating frequency of 148 MHz. The total system power consumption considering the mixed-signal circuitry, the digital processor, and the passive RRAM array is 307 mW. The maximum theoretical throughput is 2.6 GOPS at an efficiency of 8.5 GOPS/W.

Sensitive operations (e.g. control-flow transfers) are attractive targets for attackers. To protect them from being hijacked, we propose a new solution ROLoad to guarantee the integrity of their operands, which are loaded from (potentially corrupted) memory. We extend the RISC-V instruction set, implement an FPGA-based prototype of ROLoad, and then demonstrate two specific defense applications. Results show that this solution only costs few extra hardware resources (< 3.32%). However, it could enable many lightweight (e.g. with overheads less than 0.31%) defenses, and provide broader and stronger security guarantees than existing hardware solutions, e.g. ARM BTI and Intel CET.

RISC-V is an open source instruction set architecture (ISA) based on the principles of Reduced Instruction Set Computing (RISC). High-level synthesis (HLS) can automatically synthesize high-level specifications (such as in C or C++) into low-level RTL specifications for efficient implementation in application-specific integrated circuits (ASIC) or field programmable gate arrays (FPGA). This article proposes a method to implement CPU based on HLS. Based on the RISC-V architecture, the processor is designed using C language and synthesized into RTL code through HLS. This method greatly improve the speed of design and reduce the manpower required for design. In addition, by using Universal Verification Methodology (UVM) to build a verification platform to verify the RTL code, the synthesized RTL code is reliably and fully verified.

Improvements in semiconductor technology enabled smaller feature sizes, better clock speeds, and high performance. Improvements in computer architectures were enabled by RISC architectures and efficient high-level language compilers. Together, we have enabled customized computer architectures from system-on-hips to powerful GPUs and high-performance processors. Users need that the CPU should be able to access unlimited amounts of memory with low latency. The cost of fast memory is multi-fold compared to lower speed memory. Another characteristic of CPU memory access is principle of spatial and temporal locality. The solution is to organize the memory into hierarchy by caching data at different levels. Section 12.3 covers cache basics in detail. All the memory addressable by CPU need not be in physical memory due to space and cost. It can reside in disk. The address range is mapped by virtual memory manager. Virtual address constitutes the page number and the offset within the page. This page is placed in the physical memory in the free page slot available. This is indexed in the page table. Thus, virtual memory is mapped into physical memory. Section 12.4 details the virtual memory management in detail. RISC stands for Reduced Instruction Set Computer. The clock per instruction (CPI) is one in RISC. This architecture uses optimized set of instructions executed in one cycle. This allows pipelining by which multiple instructions can be executed simultaneously in different stages. RISC has several registers; instruction decoding is simple and simple addressing modes. Section 12.5 explains RISC architectures in detail. An efficient implementation of instruction execution is to overlap the instruction executions by which each hardware unit is busy all the time. Section 12.6 explains in detail this concept of pipelining and hazards are controlled in the architecture. Several advances in pipelining architecture have been developed. But the performance improvements get saturated with new constraints and issues in implementation. When a single instruction operates on multiple data elements in a single instruction cycle, the instructions are called Single Instruction Multiple Data (SIMD) instructions. Section 12.7 introduces data-level parallelism with vector processing. Section 12.9 introduces Single instruction Multi-threading (SIMT) in GPUs. We can exploit certain type of programs where they are inherently parallel and have very little dependence. We call them as threads of execution. Thread-Level Parallelism (TLP) is explained in detail in Sect. 12.10. FPGA-based technology has made system-on-chip designs a cake’s walk. Systems with high-performance requirements are possible with hardware configured to such requirements. Temporal re-configuration in FPGAs mimicking DLLs in software has made re-use of same FPGA fabric for just-in-time “use and throw” hardware blocks. Section 12.11 covers reconfigurable computing in detail. After reading this chapter, readers will be able to understand internal architecture of any processor which helps in selecting a processor for individual requirement.

International audience; Recently, several Fault Attacks (FAs) which target modern Central Processing Units (CPUs) have emerged. These attacks are studied from a practical point of view and, due to the modern CPUs complexity, the underlying fault effect is usually unknown. Only few works try to characterize them at the Instruction Set Architecture (ISA) level. In this article, we apply a state-of-the-art faults model characterization approach on modern CPU to evaluate the fault model on two different CPUs from different architectures with the same injection mediums. We target the CPU of the Raspberry Pi 3 (ARM) and an Intel Core i3 (x86) and perturbing them with ElectroMagnetic Fault Injection (EMFI). From the ISA point of view, we disclose a similar fault model on each component. Additionally, we evaluate a widely used complex software, OpenSSL, against this fault model.

One key aspect to be considered during device testing is the minimization of the switching activity of the circuit under test (CUT), thus avoiding possible problems stemming from overheating it. But there are also scenarios, where the maximization of certain circuits' modules switching activity could be proven useful (e.g., during Burn-In) in order to exercise the circuit under extreme operating conditions in terms of temperature (and temperature gradients). Resorting to a functional approach based on Software-based Self-test guarantees that the high induced activity cannot damage the CUT nor produce any yield loss. However, the generation of effective suitable test programs remains a challenging task. In this paper, we consider a scenario where the modules to be stressed are sub-modules of a fully pipelined processor. We present a technique, based on an evolutionary approach, able to automatically generate stress test programs, i.e., sequences of instructions achieving a high toggling activity in the target module. With respect to previous approaches, the generated sequences are short and repeatable, thus guaranteeing their easy usability to stress a module (and increase its temperature). The processor we used for our experiments is the Open RISC 1200. Results demonstrate that the proposed method is effective in achieving a high value of sustained toggling activity with short (3 instructions) and repeatable sequences.

MIPS-based RISC processor has a wide range of applications because of its low power consumption and high-speed performance. Here a design of Pipeline based MIPS processor is proposed using the forwarding and stalling process. A pipeline is used to improve each stage’s utilization factor and improve the overall performance of MIPS. A pipeline-based MIPS processor is presented here and has different five processing stages instruction fetch (IF), instruction decode (ID), execution (EXE), memory (MEM), and write back(WB). The data hazard solving technique is achieved by using the method as mentioned above. The design had been synthesized and simulated with the help of the Xilinx Vivado tool and implemented in the Virtex ultra scale board, and the total consumption power of 0.999 W is measured.

RISC V is an open-source ISA that is used to design the processor and the coprocessor architecture. For fulfilling the requirement of matrix multiplication, a low power and highperformance multiply and accumulate unit has been designed using a modified booth multiplier and carry look-ahead adder. Multiply and accumulate coprocessors are commonly used in all AI/Machine learning, neural network and DSP applications. Further, coprocessor designed here is capable to perform the matrix multiplication for the finite impulse response filter. Development of the low power devices is another challenge. Leakage power plays a significant amount to power dissipation in the CMOS circuits. Power gating methodologies like isolation cells, retention cells and header switches are applied to the logical circuit to reduce the leakage power of the device. The complete architecture is verified for the functionality as well as for the ASIC flow synthesis has been done for different library files. The low power analysis of design is performed through unified power format (UPF) file. The dynamic power reduces by 85.5% after using clock gating whereas the reduction in leakage power is observed to be 40 %.

This paper discusses the previous research on various 16-bit, 32-bit RISC processors with its architecture and high-speed with minimal energy consumption. This study found that the pipeline has five stages and number of instructions has been created for such processors. This study may act as a benchmark to use particular method as per one's available resource. Also, after proper analysis of each of these methods, the scope for further development will increase that helps to create a space for new research.

The electronic devices play a decisive role in the realm of medical applications. The analysis of medical images and axial tomography scanners are uses high performance processors. There is plenty of micro-controller intellectual property (IP) available for the development of ASICs, however these are tied to restrictive, expensive licenses and typically not reliable and open for customization. The reliability being a primary concern the RISC-V core aiming to development of a scalable open instruction set architecture (ISA) for medical applications. In this paper designed and implemented the 32-bit low power RISC-V based system core from RTL to GDSII. The functional verification of 32-bit five stage RISC- V system core is caried out in NC Launch tool and generated the gate level netlist using 180nm technology library file in the Genus tool. The static timing analysis is caried out for setup and hold timing analysis in the Cadence Tempus Timing Signoff tool. The floor planning, placement and routing of 32-bit RISC- V processor is implemented on Innovus tool. The area, power and timing reports are generated at each stage in the physical design. After carrying out pre-clock tree synthesis, post clock tree synthesis and post routing of circuit, obtained the optimized results for arrival timing 9.868ps, power is 3.793mW and area is 72409.1 µm2.

The main purpose of this paper is to design, verify and implement 16_bit RISC (Reduced Instruction Set Computer) processor that can be used for many embedded applications. The basic modules of this processor are programmed and simulated using Verilog HDL (Hardware Description Language), and implemented on Cyclone IV FPGA (Field Programmable Gate Arrays). Compared with general CPU it is not merely simplified the instruction set system but also make the computer structure simpler and more rational through simplifying the instruction system. Thus, the operating speed is highly improved. RISC adopts hardwire logic instead of micro-program control to realize its sequential control signals. The speed of control sequence generated is much faster than using micro-program control because it has saved the time of fetching microinstruction. The philosophy of RISC design presented here favors a smaller and simpler set of instructions. Those instructions take the same amount of time to execute. The philosophy of our design architecture was to keep the instruction set very simple. This in turn implies that addressing modes supported by instruction set a further streamlined compared to CISC (Complex Instruction Set Computer) architectures. Avoiding such addressing modes must be kept to minimum, which leads to the instructions that can be executed effectively in eight clock cycles.

In many aerospace networks based on the SpaceFibre standard, there is a need to transfer information about events occurring in various network nodes (terminal nodes, routers) for processing to other nodes. For example, information about faults during operation should be transmitted to a node performing system administration functions. In different networks, the set of events, information about which must be transmitted, the level of criticality of events for the functioning of the system, may be different. The required transmission characteristics may also vary. The SpaceFibre standard includes several mechanisms for transferring information about events from sources (terminal nodes and routers) to handler nodes. Different characteristics can be achieved (guaranteed delivery, guaranteed delivery time, the ability to transfer additional parameters, network load) with using different mechanisms. When designing a specific network, the system developer should be able to determine for each terminal node and router which events should be transmitted for processing to remote nodes and using which mechanisms this should be done. Terminal nodes and routers are developed as universal devices (systems-on-a-chip), which should provide the ability to send information about various events using various mechanisms. However, there are usually limits on the time that elapses between the occurrence of an event and sending information about it. Implementation overheads (area) are generally tightly constrained. The article proposes approach to designing an reconfigurable Event transmitting manager based on the RISC V ISA. For the proposed variants of implementation, the achievable time characteristics and overhead costs are evaluated.

This paper presents design techniques and measurement results of a radiation-hardened mixed-signal microcontroller system-on-chip (SoC) dedicated to fully-customized nanosatellites for the civil active space debris (ADR) cleaning missions. The design requirements are firstly given. The architecture of an on-board computer (OBC) is then described. A radiation-hardened-by-design (RHBD) SoC is proposed for such applications to obtain a long operational period. The proposed SoC is composed of a dual-modular redundant (DMR) 16-bit RISC processor, a 1 kB SRAM, a 12-bit pipelined SAR ADC, a 12-bit current-steering DAC and an on-chip clock generator. The radiation-hardened-by-design techniques are adopted to resist the total-ionization-dose (TID) effects. An SoC prototype is designed and fabricated in 180 nm CMOS process. The electronical performance of devices-under-test (DUTs) has been measured based on a customized mother-daughter board. The performance of the proposed SoC meet the requirements of the nanosatellites. Furthermore, the TID radiation effect experiment is performed. It indicated that the proposed SoC can resist the total dose of more than 300 krad (Si) at the dose rate of 50 rad (Si)/s.

The paper deals with automatic software-based test generation for processors as basic blocks of current complex systems on chip and embedded systems. Testing processors needs continually new test generation methods, algorithms and test application techniques for their verification, manufacture and infield testing and reliable life-time run. The functional tests of processors are mainly generated over an instruction set architecture and processor model description. Such types of tests are serving as additional tests to structural testing or as tests used in verification. They run in similar form and frequency as real programmes. Such tests are categorized as the software-based self tests. A metric for quality evaluation of the software-based tests is obviously provided by code coverage of a processor model. A functional test generation method is based on VHDL model of processors and genetic algorithms with using various evolutionary strategies. The contribution to the SBST methods based on GAs using the latest defined ES was identified. Functionality and effectiveness of the developed methods were evaluated in the implemented system AGenMIX with enhanced function of genetic algorithms computation over three types of RISC processor.

Miniature gas detection system is desirable for many applications. In this brief, we propose a fully integrated nose-on-a-chip for mobile phones and wearable devices. The chip has 36 on-chip sensors, a 36-channel adaptive interface with an integrated programmable amplifier, a four-channel frequency readout interface, one on-chip temperature sensor, a successive approximation analog-to-digital converter, a scalable learning kernel cluster, and a reduced instruction set computing core with low-voltage static random-access memory. This chip is fabricated using the TSMC 180-nm CMOS process and consumes 2.6 mW at 1 V. on-chip temperature and humidity sensors are included in this system for acquiring environmental information. An environmental compensation algorithm based on common principal components analysis is also implemented for high-accuracy odor classification. This fully integrated nose-on-a-chip provides promising results for odor detection and classification for use in mobile and wearable device applications.

Reduced Instruction Set Computing (RISC) processors have wide selection of applications performance on speed and better cache memory. The advanced RISC microprocessors are extensively used for many of the complicated systems. Reduced Instruction set Computing (RISC) is a CPU (Central Processing Unit) design mechanism that displays fundamental instruction set and performs better after comparison with the other microprocessor architecture and has the ability to perform commands per instruction through microprocessor cycles. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. Building of a fully synthesizable 32-bit RISC processor with Fetching unit, Decoding unit, Data and instruction memory, and Execution unit. The RISC Processor design is synthesized and implemented using Xilinx ISE Tool and simulated using I-sim. A 32-bit RISC is simulated and checked through VIO IP cores. We can use debug feature to drive and monitor signals that are present on the real hardware. This work is intended with Verilog HDL and implemented with the help of development board using Artix-7 FPGA device. The outcomes of performance are evaluated in terms of area, timing performance and maximum frequency of operation. The RISC processor compares earlier comparable architecture with efficient developments.

The reduced instruction set computer, or RISC, is a microprocessor that executes small and similar instructions that execute in about similar time. The objective is to reduce the complexity of instructions which in turn reduces the cost, cycle time and the operating power. Though the 16-bit RISC has been around since 1970s, it has not been up to the mark and has posed a significant number of technical barriers. This was the very reason for the development of 32-bit and 64-bit RISC processors and the concept of pipelining. In this paper, our objective is to study behavioral model of 16-bit and 32-bit RISC processor and their independent instruction sets. The 16- bit RISC processor is a non-pipelined Harvard architecture-based CPU having separate data memory and instruction memory. The 32-bit RISC is a pipelined processor borrowing its implementation strategies from MIPS architecture. The processors include GPRs (General Purpose Register) and Flag registers (Carry, Zero etc.). The model discussed will simulate optimized Multiplier algorithm and will try to optimize the data path since Arithmetic and Logical operations consume more power along with high execution delay. The paper aims to draw a comparative study between the models based on their instruction sets and performance elements such as speedup, power dissipated etc. The individual models have been designed and simulated and have been finally integrated in a top-level module via XILINX ISE Design suit 14.7 along with power analysis.

With an ever-increasing usage of electronic controllers in various disciplines that could be attributed to Industry 4.0, Internet of Things (IoT) and quick shift in computational paradigms, a demand for high code density and faster controllers are expected at the diversified nodes that improve energy efficiency without performance penalty. RISC-V is an open-source Instruction Set Architecture (ISA) which is designed with modularized extensions, that enables to design processors with a provision of individual extension evaluation helping in the design of low-power and secure embedded controllers. Bit manipulation is one of the key operations performed in domains such as Cryptography, Communication and Networking protocols, Digital Signal Processing, Bioinformatics etc., which are currently implemented using RISC-V standard instruction set. This paper implements the ‘B’ extension of RISC-V that hosts instructions specific to operate at bit-level manipulations, which is absent in ratified unprivileged ISA manual. A quantitative analysis is performed to assess the impact of Bit Manipulative Instructions (BMI) in size and speed improvements using the Embench ™ benchmarks against the standard instruction set ‘IMAC’ under the RV32 configuration. The results show significant improvements, with some programs achieving a speedup of 28 % and size reduction of 20 %.

Designing the ISA (instruction set architecture) is a very critical activity in the entire ASIP (application-specific instruction set processor) design process. There is a long history of using automated tools that suggest custom instructions based on an analysis of the data flow graphs (DFGs) of target programs. Such approaches often create an ISA that is overspecialized for a small set of applications and they often suggest a plethora of custom instructions that cannot be practically implemented. A survey of recent work indicates that adding custom instructions to freely available ISAs such as RISC-V still relies on bespoke analyses and institutional memory. In this paper, we focus on such modern applications, where we only need to add a few instructions to an existing ISA such as RISC-V. The aim is to either supplant or complement the extensive manual analysis that goes into such decision making. We propose an unconventional approach that uses novel visualization techniques to first understand the impact of different ISA features by comparing the execution of the same program using different popular ISAs: both RISC and CISC. Our novel graphical methods provide simple and intuitive explanations for differences in performance across ISAs for the same micro-architecture. Moreover, we can use this information to pick desirable instructions from other ISAs and evaluate their impact when they are incorporated. We show examples where we are able to increase the average performance by 16.5 % for 6 SPEC-2017 benchmarks by just adding 2–10 extra instructions in the basic RISC-V ISA. The performance gain is comparable with state of the art custom instruction generators. Our tool, ISAMod (ISA Modify), achieves this using a very simple and intuitive approach. It has the potential to prove itself as a vital part of the overall design flow and can reduce reliance on institutional memory to a large extent.

In this paper, we propose a method to directly describe the RTL structure of a pipelined RISC- V processor with cache, memory management unit (MMD) and AXI bus interface using C++ language. This processor C++ model serves as a near cycle-accurate simulation model of the RISC- V core, while our C2RTL framework translates the processor C++ model into cycle-accurate RTL description in Verilog-HDL and RTL-equivalent C model. Our design methodology is unique compared to other existing methodologies since both the simulation model and the RTL model are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor which runs Linux OS on an FPGA board as well as significantly short simulation time of the original C++ processor model and RTL-equivalent C model compared to commercial RTL simulator.

[EN] The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor., © 2021 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

The keyword RISC stands for reduced instruction set computer. RISC architecture has become an important part of designing processors. This chapter discusses the designed processor using the Harvard architecture. This architecture has a different memory for data and instructions. Reduced complexity, a greater number of simpler instructions, pipelining and load–store architecture are the main advantages of this architecture. FPGAs have become of great importance to verify our proposed design. In this paper, Spartan 3E starter kit by Xilinx is used to perform the analysis of power and timing delays. The proposed processor has ALU unit, left barrel shifter, right barrel shifter and control unit.

Development of high performance embedded platforms concentrates on handling huge computational requirements of complex algorithm. For high ended applications, execution of the processor will shift agreeing to the code being executed. Consequent enlightening can be depending on past instruction for the execution. Due to high dynamic energy and long latency on write operations, Reduced Instruction Set Computing (RISC) processors cannot be employed for executing some applications as it execute more instructions at a time. Its other limitations are requirement of large memory cache and hardware complexity. Due to this, designing a compiler using RISC is complicated. Due to all these issues, conventional RISC processor plan endures from less performance. One of the techniques that can be used to boost the processing in such systems is the Instruction Level Parallelism (ILP). The VLIW architecture uses Very Long Instruction Word (VLIW) architecture. This architecture is one of the promising alternative work which provides a great capabilities within an energy budget. Low power consumption and less hardware complexity are some of the advantages of VLIW processor when compared to RISC processor. However, the overall power consumption taken by the register file of this VLIW architecture is very critical. Result from the centralized resources and global communication implies that the traditional VLIW design do not scale efficiently due to the bottlenecks problem. In this paper, a design of processor to scale down the leakage energy of the register files. The proposed work also minimizes the overhead of the added hardware without performance degradation and resolves the issue conflicts among multiple threads.

Trusted Execution Environment (TEE) becomes a popular security extension on current CPUs (e.g., Arm Trust-Zone, Intel SGX, and RISC-V Keystone), but each TEE has its original SDK and cannot keep software portability. GlobalPlatform (GP) defines the general APIs named “TEE Internal APIs”, and smartphones mainly use them. In addition, the implementation of GP API assumes a Trusted OS, and some TEEs cannot implement it directly. Furthermore, some TEEs offer Enclave Definition Language (EDL) for secure communication between a normal application and a trusted application, which is not assumed by GP APIs. In order to solve these problems, we propose a library implementation of GP TEE internal APIs on each TEE SDK. We selected GP APIs for architecture-dependent or independent (e.g., secure storage and time). The architecture-independent APIs require the help of Linux or can be implemented efficiently with CPU-specific instruction. They are implemented as same as possible on each architecture. The library is designed to fit for each EDL (i.e., “edger8r” on Intel SGX “keyedge” on RISC-V) and keeps the communication security. The library is implemented on Intel SGX and RISC-V Keystone. The performances are measured and compared with the OP-TEE which is a trusted OS style implementation on Arm TrustZone. The comparison shows the feature of each implementation.

Fast, reliable, and secure data processing is critical in the Information Technology (IT) sector as it is an indispensable requirement of all the growing technologies. Achieving this requires handling large amounts of data and massive computing power. Emerging technologies use devices under low-performance environments, such as raspberry-pi, which require highly efficient databases under low computing power. Inappropriate selection of databases leads to considerable resource wastage in numerous ways, such as waste of time, cost, and energy. The selection of a reliable, user-friendly database compatible with low-performance environments will downplay the energy requirement and cut down applications' carbon footprint. Thus, this study was conducted to compare the performance and query cost of using ClickHouse and MySQL databases as column-oriented and row-oriented databases in a low-performance environment. The effectiveness of using column-oriented or row-oriented databases with large amounts of data at different platforms was analyzed. The study was conducted by running different queries using an automated PHP script and checking the execution time, processing power, disk I/O, and memory usage for each query. The study was conducted with a virtual Linux environment of 1024MB RAM, 1.8Ghz single processor, and 25Gb storage, representing very low computing power, even lesser than the recommended minimum requirement of ClickHouse and MySQL databases. Both databases performed well in the above mentioned environment. Our experimental results show that ClickHouse execution time and disk write speed is tremendously low compared to MySQL. To obtain this performance, ClickHouse used more CPU processing power and memory utilization than MySQL.

Exciting times in hardware design are upon us. Spearheaded by the RISC-V ISA, and the recent DARPA POSH/IDEA program which focuses on both open source IP and open source CAD, a large number of open source HW projects are underway. Academics are increasingly releasing their code online. Many agile open source HW projects envision a hypothetical user that may not actually exist. To acquire real users, we must be pragmatic about what kinds of systems our HW will go into and focus on the roadblocks unique to those systems.

With the advent of the Internet of Things, embedded systems have become widely used in various fields. Concurrently, the security of these systems has become a concern for many. However, security features that are already available for high-end systems have not been provided in low-end embedded systems due to its negative impact on cost and power consumption. Thus, to increase security with low overhead, many studies to implement the memory isolation approach to these systems have been conducted. However, existing techniques for this approach have suffered from problems in terms of scalability or performance. To mitigate such problems, we present RIMI, a new instruction extension to provide memory isolation in embedded systems. Thanks to instructions in RIMI, we can implement an instruction-level memory isolation where the access permission is bound to each memory and control transfer instructions. We implemented the RIMI prototype on a RISC-V architecture, which is a prominent open-source instruction set architecture (ISA). Our evaluation results show that existing security solutions, i.e., shadow stacks and in-process isolation, can be efficiently implemented with RIMI.

Post-quantum cryptography has emerged as a very attractive research topic due to the recent advancements in the development of quantum computers. Among the different available post-quantum public-key algorithms, Supersingular Isogeny Key-Encapsulation (SIKE) has posed a unique design challenge due to its resource intensive arithmetic but is characterized by small key sizes. Existing implementations of SIKE either focus on dedicated accelerators on FPGA platforms or on assembly optimized software implementations on ARM. A full FPGA implementation, though offering low latency and high performance, suffers from the disadvantage of having a large area footprint and a low flexibility. On the other hand, a pure software implementation has lower performance compared to FPGA implementations. In this paper, we propose hardware/ software co-design methodologies for SIKE and integrate a redundant number based finite field accelerator into two microcontroller platforms based on ARM and RISC-V. The result shows that our implementation on ARM Cortex-A9 enhanced with a field accelerator offers significant speedup in terms of clock cycles when compared to standalone software implementations on ARM32 and ARM64. Moreover, to show how the communication overhead between processor and accelerator can be mitigated, we integrated the finite field accelerator directly into the core of a RISC-V processor. To the best of our knowledge, this is the first design that applies hardware/software co-design methodologies to implement SIKE on ARM and RISC-V platforms. Our proposed design requires 65500 K clock cycles to execute SIKEp434 on an ARM Cortex-A9 processor. On RISC-V, our proposed design requires only 36900 K clock cycles.

An efficient instruction-based software behavior model is proposed to fully utilize the benefits of high-performance cache. This new model, which is established using process algebra, is hardware-aware (e.g., instruction set). To examine the benefits of our proposed software behavior model, an embedded RISC system is chosen in a case study, where our proposed software behavior model achieves an accuracy of more than 96% and helps to improve the cache hit rate by over 5%.

With the rapid development of Internet of Things technology, smart home products begin to come into people’s life and gradually become an indispensable part of people’s life. The popularity of smart phones and other devices has also greatly promoted the development of smart home. Combined with the characteristic of smart home, this paper proposes a remote monitoring system for smart home based on the RISC-V (RISC: Reduced Instruction Set Computing) processor. The open RISC-V ecosystem rises rapidly. It has become an important innovation point in the field of Internet of Things and edge computing. We have an opportunity to get rid of the technology monopoly. It is available to realize the localization of embedded products. The system makes use of the RISC-V processor and the Wi-Fi module to connect Alibaba Cloud, and performs remote monitoring on the mobile terminal. The experiment result verifies the feasibility of the system.

Many emerging applications require simple controllers that run the exact same application continuously. These include medical devices and IoTs of different nature. Because of the nature of these applications, they have to be ultra-low power and small. Most of the applications mapped onto low-power processors are computationally inexpensive, thus, amenable to be executed on a simple microprocessor. One of the problems of using a general purpose processor, is that not all of the resources are needed for a specific application, thus, there is a large potential for simplifying the processor to achieve lower area and power (static and dynamic). In addition, these processors can be specified at the behavioral level and use High-Level Synthesis (HLS) to generate the RTL automatically. This opens a window to additional optimizations as the processor can be pruned and re-synthesized at different VLSI design levels in order to obtain a smaller and more power-efficient processor. This work presents a methodology to customize a behavioral RISC processor automatically for a given workload such that its area and power are significantly reduced as compared to the original processor. Compared to previous work that customizes a given processor at the gate netlist only, our proposed method also shows significant benefits. In particular, we show that raising the level of abstraction reduces the area and power by 78.3 % and 70.1%.

We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of microprocessors without needing the knowledge of implementation details. The test covers a large class of faults and a special target is to detect Transition Delay Faults (TDF). To reduce the complexity, the processor is partitioned into Modules Under Test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, whereas for the control parts a novel functional control fault model was developed. The test is regular, represented in a compact form allowing easy unrolling during test execution. Experimental results demonstrate high Stuck-At Fault (SAF) and TDF coverage, despite the lack of knowledge of implementation details

RISC-V is free and open standard instruction set architecture following reduced instruction set computer principle. Because of its openness and scalability, RISC-V has been adapted not only for embedded CPUs such as mobile and IoT market, but also for heavy-workload CPUs such as the data center or super computing field. On top of it, Robotics is also a good application of RISC-V because security and reliability become crucial issues of robotics system. These problems could be solved by enthusiastic open source community members as they have shown on open source operating system. However, running RISC-V on local FPGA becomes harder than before because now RISC-V foundation are focusing on cloud-based FPGA environment. We have experienced that recently released OS and toolchains for RISC-V are not working well on the previous CPU image for local FPGA. In this paper we design the local FPGA platform for RISC-V processor and run the robotics application on mainstream Robot Operating System on top of the RISC-V processor. This platform allow us to explore the architecture space of RISC-V CPU for robotics application, and get the insight of the RISC-V CPU architecture for optimal performance and the secure system.

With the increasingly serious haze disaster, the development of dehazing technology is highly concerned. But the current software dehazing algorithm suffers from too high computational complexity. We selects the algorithm based on dark channel prior with sky preservation [1] as the base software algorithm, and a hardware accelerator is designed to simplify the data transmission process and optimize the data processing. The whole operation simulation of the accelerator is realized in NC-Verilog hardware design environment. The accelerator can achieve 75fps@640x480 video dehazing under 0.18$\mu$m CMOS technology. It can be applied to driving assistance and surveillance system.

An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET $ \lt 101.5$ MeV-cm $^{2} /$ mg), validating the effectiveness of the methodology.

The reduced instruction set computing (RISC) architecture is a free and open Instruction Set Architecture (ISA), which enables a new era of processor innovation through open standard collaboration. It directly challenges several well-established processor families such as intel x-86, Motorola 68k processor. To thrive an RISC-V ecosystem, the core suppliers need an independent verification solution to ensure that their designs are compliant with the ISA specification. Verification of RISC-V designs become challenging due to their optional features, implementation flexibility, and provisions for customer extensions. Hence, a thorough verification is essential to compete successfully against the established processor families. Automation is the key for reducing the time taken for the processor verification. This paper provides a way to develop an automated tool ATGP_RISC-V, which uses the same arguments to run all instruction generators. This helps in verifying the processor in an efficient way by reducing the time taken to manually compare the test results.