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Total-ionizing-dose (TID) effects and low-frequency noise are evaluated in advanced bulk nMOS and pMOS FinFETs with SiO2/HfO2 gate dielectrics. Otherwise identical devices built with and without through-silicon via (TSV) integration exhibit threshold voltage shifts of less than 25 mV and changes in maximum transconductance of less than 1% up to 2 Mrad(SiO2). TSV integration negligibly impacts threshold shifts and degradation of subthreshold swing and $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratios. Similar low-frequency noise magnitudes and frequency dependencies are observed before and after TID irradiation for each device type. Effective densities of the near-interfacial electron traps responsible for the noise in the nMOS devices increase as the surface potential moves toward midgap, while effective densities of the hole traps that cause the noise in the pMOS devices increase as the surface potential moves toward the valence band edge.

We report laser-based fault isolation methodologies for the localization of open and short failures in $1 \times 5\,\,\mu \text{m}$ via-last through-silicon via (TSV) structures for 3-D system-on-chip (SoC) integration. Due to the photosensitive TSV interconnect capacitance, observation of the photocapacitance response enables nondestructive localization of metallization ruptures. A light-induced capacitance alteration (LICA) measurement is demonstrated on an open failed $1 \times 5\,\,\mu \text{m}$ TSV chain structure with a manufacturing defect. We validate our measurements with active voltage contrast imaging in the scanning electron microscope (SEM) and focused-ion beam (FIB) cross sectioning. Second, TSV dielectric defects generating leakage current between TSV and substrate (i.e., short defects) are detected and localized by sensing the laser-induced TSV photocurrent. An optical beam-induced current (OBIC) measurement is demonstrated on electrically overstressed TSV array structures whereby multiple TSVs are configured in a parallel arrangement. By applying a selective substrate removal process, we can expose the full TSV array and perform optical and tilted SEM inspection and reveal pinhole defects in the TSV liner. We further investigate the effect of breakdown energy on the pinhole formation, relate electrical measurements to SEM inspection, and confirm our results by FIB cross sectioning.

A binary wafer-to-wafer stacking scheme is advantageous over a sequential approach in terms of manufacturing cost and its impact on the stacked system yield. In this paper, such a binary wafer-to-wafer stacking flow is demonstrated. Two full thickness wafers are paired Face-to-Face using a $2\mu \mathrm{m}$ pitch hybrid bonding technology, followed by top wafer thinning to $2\mu \mathrm{m}$ . The Face-to-Face connections are fed through to the thinned top wafer surface by means of a $1\mu \mathrm{m}$ diameter by $5\mu \mathrm{m}$ deep via-last TSV. $2\mu \mathrm{m}$ pitch hybrid backside pads are realized on top of these via-last TSVs, at the same time levelling out and planarizing the backside of the Face-to-Face bonded wafer pairs. Two $\mathrm{N}=2$ Face-to-Face bonded wafer pairs are Back-to-Back hybrid bonded to each other, realizing an $\mathrm{N}=4$ multi-tier wafer stack. The N4 top wafer is thinned to $5\mu \mathrm{m}$ , revealing the nails of $5\mu \mathrm{m}$ diameter by $8\mu \mathrm{m}$ deep via-middle TSVs, implemented on this N4 wafer prior to the Face-to-Face bonding. An N4 backside passivation and an aluminum METPASS module finishes the multi-tier $\mathrm{N}=4$ process flow. The paper describes the realization of the above explained integration flow. Several process challenges are extensively elaborated. Electrical results, featuring 100% yielding Back-to-Back kelvin and interwoven chains connections, demonstrate the maturity of this multi-tier $\mathrm{N}=4$ binary stacking process.

This paper demonstrates the fabrication of a reliable 0.7µm diameter and 5µm deep (0.7x5µm) via-last module, fitting a 1.4µm TSV pitch. Enabling sub-micron TSV diameters requires a thinner photo resist, however still withstanding the top passivation dielectric etch, the deep silicon etch and the bottom dielectric etch. The actual TSV silicon diameter is 0.8µm just below the top dielectric hard mask, but reduces to 0.7µm in the middle and to 0.65µm at the bottom of the via. The bottom dielectric tri-layer, consisting of an STI oxide, a thin SiN and a PMD oxide layer, is etched using a dedicated three step selective etch recipe. A thin ALD TiN embedded barrier is implemented, assuring good TSV reliability. An alternative and scalable protection of the oxide liner at the top of the TSV during bottom liner etch is worked out. It makes use of an APF strippable amorphous carbon film. Despite the sub-micron TSV diameter, a conventional PVD Ta barrier and PVD Cu seed is still maintained. Discontinuities in the PVD Cu seed are repaired by using a 30nm thin alkaline ECD seed layer enhancement (SLE), resulting in a conformal copper seed all over the TSV and ensuring void less ECD copper fill. Electrical results prove the maturity of this 0.7µm diameter, 1.4µm pitch via-last module. The connectivity of the TSV, from wafer front to back side, has been checked by means of kelvin and daisy chain structures, showing 100% yield and low spread on the measured resistance values. High breakdown voltage of the TSVs is obtained. The integrity of the oxide liner all over the TSV sidewall is proven by means of IV-controlled reliability measurements (IVCTRL). The breakdown voltage Vbd has very little dependence on the applied stress voltage ramp rate, resulting in high field accelerating factor γ, confirming the high TSV liner/barrier reliability.

The effects of copper permanent deformation during thermal cycles in backside through-silicon via (TSV)-last fabrication process are studied using an advanced 3-D simulator. The plasticity and creep model parameters are chosen to match experimental data. Two sets of different TSV configurations and back end of line (BEOL) layouts are utilized to examine TSV reliability, BEOL reliability, and front-end device performance after postplating thermal excursion. The results indicate that the copper plasticity deformation affects TSV stress distributions for TSV-last fabrication process. The configuration employing a thicker liner made of a softer material shows better TSV and BEOL reliability and lower TSV stress-induced device performance impact. It is also observed that the BEOL layout near the TSV edge needs to be optimized as the BEOL structures in this region experience larger mechanical stress and lower reliability.

In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3µm and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctrl) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100?C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS oxide liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD oxide liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications. Display Omitted Reliability of two 3×50µm TSV compatible metallization schemes is investigated.TDDB data are impacted by interactions between Si scallops and liner conformality.The scalable one shows more sensitivity to local field enhancement at high field.Their performance at operation fields meets standard reliability specifications.

A 1×5μm via-last TSV module is presented, coping with the reliability challenges imposed when exposing the metal landing pad during the liner opening etch at the TSV bottom. Two approaches are presented. A dedicated soft-landing liner oxide dry etch step is developed, eliminating the re-sputtering of copper on the TSV sidewalls. An embedded barrier is integrated, blocking the diffusion of any eventually re-sputtered copper of the landing pad. The obtained via-last TSV reliability is high for both approaches and comparable with via-middle TSV modules.

This paper presents face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination a novel 1µm diameter via last connection between top and bottom wafers, called "hole-in-one TSV". This scheme reduces besides the interconnection pitch and also the number of processing steps. The hole-in-one TSV is introducing an innovating integration modification. With the introduction of a cavity etched in the top wafer prior to W2W bonding, the via last etch process is simplified. The etch time of the dielectric part of the TSV etch is heavily reduced, minimizing the over etch time on the top landing metal to open the landing wafer's metal pad. Critical integration steps like CMP processes, wafer bonding and thinning to 5µm Si thickness are highlighted, together with alignment tolerances and connectivity yield between the bonded 300mm Si wafers.

Process-induced planar MOS capacitor reliability degradation is investigated in both via-last and via-middle through-silicon via (TSV) integration flows, with the capacitor electrically connected to the TSV. The leakage current and the breakdown voltage of the MOS capacitor are characterized to detect possible dielectric degradations caused by the electric charges generated during plasma-based processing steps: in the via last flow, during TSV dielectric liner dry etch and PVD metal barrier deposition steps; in the via-middle flow, during the backside TSV dry-etch reveal step. The effectiveness of a protection PN diode in preventing the MOS degradation is also evaluated.

For 3D chip stacking using via-middle Cu Through Silicon Via (TSV), the TSV liner/barrier reliability needs to be preserved during the whole backside process flow. In this paper, the impact of backside process on the via-middle TSV liner/barrier material reliability is investigated and a reliable liner/barrier implementation is proposed for high aspect ratio via-middle TSV integration process.

An advanced TSV metallization scheme, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling is presented. Because of the high conformality of the WN barrier and NiB seed, very thin layers can be deposited, reducing the manufacturing cost significantly, while still guaranteeing continuous barrier/seed layers all along the TSV sidewall to the bottom of the TSV. 3 × 50μm via-middle wafers, processed with this metallization scheme, are further processed through the thinning module, by using temporary bonded carriers, the backside passivation module and a copper RDL module by using a semi-additive process. The TSV resistance is measured between the 5μm thick RDL copper layer at the back side and the METPASS aluminum layer at the wafer front side. Low spread and high yield is obtained on the resistance data distribution of both single kelvin and daisy chain structures. The same metallization scheme is successfully scaled to a 2μm diameter and 40μm deep via-middle module. The conformal deposition of the barrier and the seed layer enables further scaling down to aspect ratio 20:1 through silicon via's with 5μm pitch, still ensuring the void-free bottom up copper fill by electroplating. The integrity of the liner/barrier system against Cu diffusion from TSV to silicon has been verified using the established controlled I-V method. Field acceleration factors, extracted in both copper-confined and copper-driven regime, indicate good TDDB reliability of this advanced 2 × 40μm TSV middle module.

Foundry customers and makers of leading-edge devices are evaluating through-silicon via (TSV) for next-generation three-dimensional (3D) packaging. Scaling the diameter of the TSV is a major driver for improving system performance and cost. With smaller TSV diameters, back-to-front overlay becomes a critical parameter because via landing pads on the first metal level must be large enough to include both the TSV critical dimension (CD) and overlay variations. In this paper we investigate the long term capability of a Dual Side Alignment (DSA) lithography system for printing 5 μm and smaller TSV features. DSA lithography is used to pattern the TSV feature, and Stepper Self Metrology (SSM) is performed to verify the overlay after photoresist development. Multiple stepper lithography fields per wafer and multiple wafers per lot are measured to obtain a statistically significant data set for wafer lot overlay analysis. In addition, multiple wafer lots were processed and measured to establish long term overlay performance and stability. In order to independently verify the SSM overlay data, dedicated electrical structures were designed and placed on a Via Last TSV test chip. These structures allow the TSV diameter and TSV overlay to be measured electrically after lot completion. Vector plots were used to compare the SSM overlay and electrical overlay data.

Current TSV integration schemes include via-first, via-middle and via-last process flows. In this paper, a low thermal budget, 10im pitch and aspect ratio 10 (5im diameter, 50im depth) via-last TSV module is presented. The proposed via-last module is plugged in after the thinning module, with 50im thinned device wafers temporary bonded to a Si carrier, using Brewer Science Zonebond® material. After the deposition of a thin back side passivation layer, the TSV lithography is performed with back-to-front alignment to the front side Metal1 pattern using a Dual Side Alignment (DSA) system, available on the Ultratech AP300. The overlay performance to Metal1, verified by dedicated software utilizing the DSA alignment system, is better than 750nm, fulfilling the requirements for a 5im diameter by 50im depth TSV module with a TSV pitch of 10im. The TSV deep-Si etch lands on the STI/PMD oxide stack. In order to prevent severe notching at the silicon to oxide interface, a soft landing etch step is introduced by tuning the etch process parameters. The soft landing accommodates as well for the total silicon thickness variation of the thinned wafers. Prior to the TSV resist strip, the STI and PMD oxide is etched, stopping just above the Metal1 landing pads. Next, a high conformal PEALD oxide liner is deposited at low temperature, avoiding local deformation of the thermoplastic temporary glue material. In order to enable electrical contact from the TSV to the Metal1 landing pads, the liner oxide is selectively removed at the bottom of the TSV by means of a directional dry etch step. To avoid any liner oxide recess at the top of the TSV, the liner is protected with a non-conformal PECVD low temperature SiN layer. This SiN layer deposits at the top part of the TSV, capping the oxide liner, but doesn't deposit deeper into the TSV. As a result, the oxide liner is cleared at the TSV bottom during the oxide liner etch, at the same time preserving this oxide liner at the top of the TSV which is protected by the PECVD SiN capping layer. Prior to the PVD Ta barrier deposition, a dedicated argon soft sputter etch with high RF bias power is applied to ensure the complete removal of any tantalum oxide interfacial layer. The PVD Cu seed is deposited in-situ with the barrier. ECD copper fill and CMP of the Cu overburden and Ta barrier material finishes the via-last module. Backside RDL, using a semi-additive process, provides the electrical contact to the TSV at the thinned wafer back side. Electrical results are shown, proving the maturity of this TSV last process scheme. The connectivity of the TSV, from wafer front to back side, has been checked by means of kelvin and daisy chain structures, showing 100% yield and low spread on the measured resistance values. Low leakage current and high breakdown voltage of the TSVs is obtained, demonstrating the integrity of the oxide liner all over the TSV sidewall.

An advanced Via-Middle TSV metallization scheme is presented, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling process. Because of the high conformality of the WN barrier and NiB seed, these layers can be deposited very thinly, reducing the cost significantly, while still guaranteeing continuous barrier/seed layers all along the TSV sidewall till the bottom of the TSV.

In high aspect ratio TSV's, the step coverage (conformality) of liner, barrier and seed is critical for both the integration and reliability. If the conformality of a deposition technique is improved, the required thickness to be deposited on the field of the wafer can be reduced. Consequently, less material needs to be removed by CMP on the field, which reduces the manufacturing cost. In this paper, the reliability of two liner/barrier/seed options, which were successfully integrated into via-middle TSV's with a diameter of 3 micron and an aspect ratio (AR) of 17 is investigated. Both controlled ramp rates (IVctri) as well as standard Time Dependent Dielectric Breakdown (TDDB) at 100°C were employed as electrical testing methods to investigate the dielectric and barrier reliability properties of the studied systems. The first studied system consists of a non-conformal CVD O3 TEOS liner, an ALD TiN barrier and a PVD Cu seed. The second studied system employs a conformal ALD liner, a thermal ALD WN barrier and an ELD NiB seed. Both studied systems show excellent reliability properties. Scalable highly conformal liners are more sensitive to local field enhancement at the high fields applied during highly accelerated tests which are far above normal operation conditions. Their performance at lower fields, however, still meets standard reliability specifications.

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

To keep up with the pace of decreasing transistor channel length, the demand for smaller pitch size is pushing 3D IC research into new approaches for stacking. As the pitch size decreases, the thickness of interconnection also decreases. During stacking, a small misalignment may lead to poor interconnection or even connection failure. This has led 3D IC research to pursue higher alignment accuracy during stacking. One such stacking approach that is being considered is 3D self-alignment. To facilitate highly accurate alignment it is also important to have good quality immediate bonding that can further reduce chances of misalignment during handling. In this work, we demonstrate a very high quality bonding between two similar dies with oxide capping layer, as well as different cleaning approach and the bonding test.

The cost of 3D process flows is one of the most important aspects for the broader adoption of 3D integration by the semiconductor industry. In this paper the processing cost of the features and components that enable 3D stacking is considered and compared. Different stacking approaches are considered: D2W, W2W and interposer-based stacking. Furthermore, the impact of processing yield and pre-stack testing is evaluated when considering the system integration cost for each one of the 3D stacking methods. In addition the size of the stacked active dies is parameterized and the effect on the system integration cost is explored. Also, the impact of pre-stack testing on interposer in relation to processing yield and the size of the stacked active dies is investigated.

Cu pumping of through silicon vias (TSV) may result in deformations of the Cu/low-k interconnect wiring above the TSVs and affect the back-end-of-line (BEOL) metal and dielectric reliability. We investigate the impact of Cu TSVs on the BEOL reliability, including stress induced voiding (SIV) of Cu vias on top of the TSV and the dielectric reliability of both inter- and intralevel low-k materials in Cu damascene interconnects. Possible solutions to mitigate the reliability risks are also discussed.

A 2D TCAD based device architecture exploration of SiGe:C NPN HBTs is presented. Two novel and one conventional self-aligned architectures are explored by process and device simulation. All these three architectures show their capability of achieving maximum oscillation frequency ( f max ) of 500 GHz for scaled layout rules.

Various isolation schemes consisting of junction isolation, silicon pedestal isolation, deep trench isolation (DTI), airgap deep trench isolation and SOI with DTI are compared in terms of thermal resistance (R TH ) and collector-substrate capacitance (C CS ). Although to some extent R TH and C CS can be traded, airgap DTI and especially pedestal isolation perform very well, because the former results in strong reduction of C CS , while the latter results in strong reduction of R TH .

A SiGe spike in the monoemitter of a SiGe:C HBT locally increases the recombination rate. The narrower energy bandgap of SiGe compared to Si increases the minority charge storage, resulting in higher recombination rate. The SiGe spike acts as a virtual contact and increases the base current. This results in lower current gain, and hence higher BV CEO . This paper studies the physical mechanism for this higher recombination rate in the SiGe spike, and it calculates the minority carrier lifetime in the SiGe spike.

A 2D TCAD based device architecture exploration of SiGe:C NPN HBTs is presented. Two novel and one conventional self-aligned architecture are explored by process and device simulation. All these three architectures show their capability of achieving maximum oscillation frequency (f max ) of 500 GHz for scaled layout rules.

We investigate the effect of the lateral scaling of an existing 200GHz single poly SiGe:C HBT quasi self aligned (QSA) BiCMOS technology upon low frequency noise (LFN). The purpose of this lateral scaling is to improve FMAX and to displace the peak fT and FMAX to lower current per unit length and our process and device simulations predict significant effects on these two quantities. Lateral scaling affects the perimeter design of the device, a region having a strong influence on the LFN behavior of the transistor. We study the impact on LFN of reducing three lateral design parameters, namely the emitter window, the width of the enclosure of the emitter window surrounded by polyemitter and the width of the enclosure of the polyemitter surrounded by the active area. Our results show that the process window, predicted by simulation and tested by DC lateral scaling characteristics, still remains available, maintaining the required HF and LFN good qualities with the scaled architecture and process.

In this work, we present the use of SSRM, an electrical characterization technique based on atomic resistance microscopy (AFM), as a verification tool for the accurate calibration of two dimensional (2D) process simulations on advanced high speed bipolar HBT devices with fT/fmax values exceeding 200GHz. The 2D HBT process simulator has been calibrated based on SIMS measurements and TEM pictures. The process simulations consider coupled diffusion of carbon and silicon point defects under several RTA conditions [1]. Kick-Out and Frank-Turnbull mechanisms model the carbon diffusion. Extended short-loop experiments under equilibrium and non-equilibrium conditions increased the accuracy of the simulations [2]. Lateral and vertical scaling of the bipolar device dimensions is an absolute requirement for obtaining current and power cutoff frequencies (fT, fmax) above 200GHz [3]. The state-of-the-art QSA HBT investigated in this work for instance has an enclosure of active area over the poly emitter of only 0.03μm. As the external base implantation, needed to obtain low base resistance, is done after the poly emitter patterning, a precise determination of the base collector junction becomes difficult but at the same time important, taking into account the interaction with the selectively implanted collector (SIC) and the importance of the base-collector junction location for the DC device characteristics. Simulations using the calibrated 2D-TCAD platform show the different shapes of the external base-collector metallurgical junction as a function of the poly emitter sidewall angle (fig 1). The vertical depth of the basecollector metallurgical junction along the STI drops from 90nm to 75nm and even 45nm for a poly emitter sidewall angle of respectively 90°, 80° and 73°. From crosssectional pictures we know that the poly emitter sidewall angle is around 80°, but so far we were unable to verify the exact position of the base-collector metallurgical junction on real silicon. A key advantage of the SSRM technique however is its capability to determine the precise location of electrical transistor junctions. The improvements in sample preparation and the introduction of full diamond probes have enabled a drastic increase of the spatial resolution down to 1-3nm [4,5], even for HBT transistors where many materials with different hardness are present (silicon, polysilicon, oxide, nitride, silicide, SiGe). Figures 2 and 3 show such SSRM plots for the QSA 0.13μm SiGe:C HBT. A comparison is shown with a 2DTCAD plot and with a TEM picture respectively. Geometrical distances and the base-collector junction can be clearly distinguished on the SSRM plots. A quantification of the key geometrical and electrical distances extracted from the SSRM data are summarized in table 1. They are compared with the TCAD values. SSRM quantifies correctly known geometrical values like for instance the nitride thickness of the emitter window and the oxide undercut under this nitride. The measured lateral and vertical electrical junction depths from SSRM correspond well with the values extracted from the calibrated 2D-TCAD platform. We conclude therefore that the 2D-TCAD process simulator is correctly calibrated. This TCAD platform will be used for future process optimization of advanced high speed HBT devices.