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Self-Aligned Multiple Patterning is one of the multiple-patterning techniques to realize sub optical lithography technology nodes. The challenges for advanced interconnect levels with multiple-patterning integration are to control both metal CD and the space between line ends. This can be associated with complicated process integration. In this paper, a novel patterning scheme, metal on metal multiple patterning integration, which significantly simplified the process steps and enabled self-aligned block (SAB), is demonstrated for a single damascene level by process emulation. This novel integration utilizes metal as the mandrel. In addition to that, in this scheme the non-mandrel metal material could be different from the mandrel metal. As a result, mandrel metal could have different electrical or physical properties than the non-mandrel metal. As an example, the mandrel metal could have better reliability to carry large current while the non-mandrel could have lower resistivity for performance.

Electromigration and resistivity of Cu, Co and Ru on-chip interconnections have been investigated. Non-linered Co and Ru interconnects can have better interconnect resistance than Cu, if the Cu liner cannot be scaled down below 2 nm in future interconnect technologies. A similar resistivity size effect increase was observed in Cu, Co, and Ru. Multi-level Cu, Co or Ru back-end-of-line interconnects were fabricated using 7 and 10 nm node technology wafer processing steps. EM in 18 nm to 88 nm wide Co lines, 18–24 nm wide Cu with a thin Co cap and 18 to 24 nm wide Ru lines were tested. The electromigration activation energies for Cu with Co cap, Co and Ru were found to be 1.5–1.7 eV, 2.4–3.1 eV and 1.9 eV, respectively. These data showed that Cu with Co cap, Co and Ru interconnects all had highly reliable electromigration.

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.

In this paper, the impact of gap-fill planarity on Multi-Self-Aligned Block, SADP (self-aligned double patterning) process for advanced optical technology nodes (7 nm/5 nm) interconnects was studied through process emulations. This study specifically focuses on the insertion of an etch stop layer (ESL) between two coatings of organic planarization layer (OPL), referred to as the tri-layer PM (pattern mask), which enables a thinner OPL for pattern transfer while adding topography correction for non-mandrel block patterning processes. This scheme reduces pillar aspect ratio for improved CD control and flop-over mitigation, as well as topography correction to mitigation false metal patterns in field regions. However, ESL could cause CD variation if it was deposited on the sidewall of spacer where it is a function of the conformality of ESL deposition.

In the attempts to push the resolution limits of 193nm immersion lithography, this work demonstrates the building of 3 metal level 56nm pitch copper dual-damascene interconnects, using Negative-Tone Development Lithography-Etch-Lithography-Etch (LELE) Patterning at line level. Line Resistance and intra-level capacitance can be affected by the double patterning integration, but a good process window has been demonstrated, showing no impact on RC performance. The introduction of a self-aligned via (SAV) process with a TiN hard-mask is able to provide a robust process window in terms of via-metal short yield at line and via level. SAV implementation at these dimensions also affects the aspect-ratio of the structures and leads to new challenges in metallization: optimized profile, without bowing or undercut, is mandatory to enable the filling of 28nm lines. The metal hard-mask has to be removed or at least faceted by erosion. This can be achieved by conventional RIE process optimization, but pushes the RIE selectivity to challenging limits. Physical dimensions on target and via chain yield have been demonstrated by fine tuning RIE process. Profile improvement can also be achieved by the introduction of new WET process, helping the removal of the metal hard-mask while being neutral to the ULK. We have demonstrated good yield and reliability with an integration using hard-mask wet removal.

Integration of high porosity low-k dielectrics faces major challenges as the porosity weakens the dielectric, resulting in severe plasma induced damage (PID) and difficulties in profile control. Post porosity plasma protection (P4) integration strategy addresses those challenges by strengthening the dielectric via porosity refill during the integration steps. Realization of P4 integration at an advanced node is nontrivial. In this paper, we demonstrate the feasibility of the P4 integration scheme in a dual damascene double patterning 48 nm pitch test vehicle with a plasma enhanced chemical vapor deposited (PECVD) k = 2.4 inter-layer dielectric (ILD). In addition, initial results of applying P4 with a PECVD k = 2.2 ILD show promise in reducing capacitance at 48 nm pitch and beyond.

48 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Ru interconnect has comparable high yield for line and via macros. Electrical results show minimal impact for via resistance and around 2 times higher line resistance. Resistivity and cross section area of Ru interconnects are measured by temperature coefficient of resistivity method and the area was verified by TEM. Reliability results show non-failure in electromigration and longer time dependent dielectric breakdown. Based on the data collected, Ru could be a metallization contender at linewidth of 16 nm and below.

We characterize integrated dual damascene Co and Cu BEOL lines and vias, at 10 nm node dimensions. The Co to Cu line resistance ratios for 24 nm and 220 nm wide lines were 2.1 and 3.5, respectively. The Co via resistance was just 1.7 times that of Cu, with the smaller ratio attributed to the barrier layer series via resistance. Electrical continuity of Co via chain structures was good, while some chain-chain shorts and leakage suggests metal residuals from the Co polish process. The Co lines and vias, fabricated using conventional BEOL processes, exhibit good Co fill by TEM, with no visible evidence of Co in the dielectric. The relatively smaller resistance increase for Co vias suggests a potential via resistance benefit, a thinner or less resistive barrier can be employed. Co line resistance will likely not be competitive with Cu until after the next technology node.

A 36 nm pitch BEOL has been evaluated for the 7 nm technology node. EUV lithography was employed as a single-exposure patterning solution. For the first time, it is shown that excellent reliability results can be obtained for Cu interconnects at these small dimensions, by using a TaN/Ru barrier system and a selective Co cap.

Multi-layer SiNO barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCN and SiN barrier films used at previous technology nodes. Combining SiCN with multi-layer SiNO barrier film provides robust Cu and O barrier properties at film thickness of ∼10–14 nm. SiNO layers in the bi-layer film help lower the dielectric constant and hence provide capacitance benefit in the integrated structures. The high breakdown SiNO layers provide benefit in the via chamfer region and improves inter-level time dependent dielectric breakdown (TDDB). Overall, the SiCN/SiNO bilayer dielectric film shows robust device reliability as compared to the state of the art barrier films.

An improvement in interconnect performance implies a reduction of the resistance-capacitance (RC) time constant. Instead of scaling the capacitance at each technology node through a reduction in the dielectric constant of the interlayer dielectric (ILD), the interconnect aspect ratios could be scaled holding the ILD fixed. In this case, the material properties of the ILD must be robust to process-induced damage and amenable to the creation of high aspect ratio features. In addition, a metallization scheme that can provide void free Cu fill in high aspect ratio features is required. Characterization, patterning, and integration results collected on such an ultra-low-k (ULK) ILD material and void free metallization is presented. A measured reduction in the resistance of a 22nm node interconnect in this ILD was observed as a function of increasing aspect ratio. The copper seed deposition process, capable of enabling the fill of even higher aspect ratio features, is also discussed.

In agreement with the ITRS roadmap, there have been several publications supporting the reduction in critical dimensions and the introduction of new materials to semiconductor processing (1,2,3). This paper highlights the observations and solutions to some of the critical material and process interactions encountered during the integration of the back end of line interconnect.

Through-Co self-forming-barrier (tCoSFB) metallization scheme is introduced, with Cu gap-fill capability down to 7 nm-node dimensions. Mn atoms from doped-seedlayer diffuse through CVD-Co wetting layer, to form TaMn O barrier, with integrity proven by vertical-trench triangular-voltage-sweep and barrier-oxidation tests. tCoSFB scheme enables 32% and 45% lower line and via resistance, respectively at 10 nm node dimensions, while achieving superior EM performance to competitive TaN/Co and TaN/Ru-based barriers.

A cost effective 28nm CMOS Interconnect technology is presented for 28nm node high performance and low power applications. Full entitlement of ultra low-k (ULK) inter-level dielectric is enabled. Copper wiring levels can be combined up to a total of 11 levels. The inter-level dielectric was optimized for low k-value and high strength. The feature profiles were optimized to enable defect-free metallization using conventional tools and processes. High yields and robust reliability were demonstrated.

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um 2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

In order to maximize Cu volume and reduce via resistance, barrier thickness reduction is a strong option. Alternative barriers for next-generation BEOL were evaluated in terms of barrier performance to O 2 and Cu diffusion, and effects on reliability. A clear correlation of O 2 barrier performance to electromigration was observed, suggesting that the key role of the barrier layer is to prevent oxidation of Cu or the Cu/barrier interface. Long-throw PVD-TaN showed superior O 2 barrier performance to alternative metals such as PEALD-TaN, thermal ALD-TaN, -TaN(Mn) and - MnN and MnSiO3 self-forming barrier.

In this paper, optimization of 1X BEOL wiring level of 7 nm node is presented. We focus on the interconnect delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on the characteristics of the 10 nm driver circuit. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, the impact of the BEOL on the circuit performance can be determined. The interconnect delay is plotted as a function of wire resistance, via resistance and capacitance. In order to better optimize the BEOL architecture, contour plots of resistance versus capacitance are presented in this paper. The result of this paper is indicating a strong dependency of circuit performance on the wiring length which is a new challenge. Optimization of BEOL architecture therefore requires a new approach which is outlined in this paper. As a result, we would like to bring this to the design community's attention.

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.

Critical parameters of low-k films were defined to keep capacitance benefit and TDDB reliability in the scaling BEOL module, according to various analyses. In order to meet the criteria of high carbon content, low porosity with small pores, and high adhesion strength with less adhesion layer, precursor and process were designed for the SiOCH with k∼2.5. The benefits in integration and reliability from the newly developed robust low-k film were verified through the trench-first integration of 80 nm-pitch BEOL modules.

Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme to investigate the feasibility of the SIT process for sub 50nm-pitch technology node. 45nm-pitch line resistance (R) and capacitance (C) simulation are performed to estimate the R-C variation for double patterning schemes. The photoresist mandrel SIT process for 56nm-pitch Cu line is investigated to develop the constant line pitch and less line edge roughness (LER). The basic electrical properties such as line open/short and via chain open/short yields are ∼100%. The 56nm-pitch R-C variation is comparable to simulated 80nm-pitch R-C variation. The SIT patterning process is a strong candidate to improve the R-C variation for sub50nm-pitch technology nodes.

A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV process and DD structure build. We present STEM cross sections of the structures after TiN HM deposition, HM open and DD RIE to determine the minimum required TiN HM thickness for the SAV process. We characterized the TiN loss for each RIE step from cross section results and defined the optimal TiN thickness for 64nm pitch interconnects. Using the optimized TiN thickness, we fabricated DD structures and compared the metal-to-via short electrical performance for SAV and non-SAV processes to show the overlay (OL) impact on shorts yield. Structures fabricated using the SAV process have excellent yield regardless of the degree of via misalignment in the SAV direction since no via CD growth occurs in the constrained SAV direction, while those processed with a non-SAV scheme show via yield degradation with increasing via misalignment. Also, with respect to misalignment in the non-SAV direction, there were no significant electrical differences between structures made using SAV and non-SAV approaches.

This work demonstrates the building of 64 nm pitch copper single and dual damascene interconnects using pitch split double patterning scheme to enable sub 80nm pitch patterning. A self-aligned-via (SAV) litho/RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. An undercut free post RIE trench profile enabled the good metal fill. Initial reliability test result and the possibility of using the same scheme for 56 nm pitch interconnects are also discussed.

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

We have demonstrated the complete copper filling of contact structures at 32 nm- and 22 nm-node dimensions with the conventional PVD only Ta(N)/Cu barrier/seed process. Copper seed process was optimized to obtain the sufficient coverage of copper along the contact hole with the sufficiently wide gap opening at the top by the use of the directional sputtering and the re-sputtering techniques. In addition, this process was implemented on fully integrated 32 nm-node device wafers and the optimized process produced sufficient performance to meet 32 nm-node requirements. The investigation also included two cases with intentional departure from the optimal conditions, one with a low thickness barrier and the other without copper re-sputtering. In both cases negative influence on front-end-of-the-line (FEOL) parameters was observed.

We used Cu contact metallization to solve one of the critical challenges for 22 nm node technology. Cu contact metallization allowed us to demonstrate world's smallest and fully functional 22 nm node 6T-SRAM [1]. Cu contact metallization was executed using CVD Ru-containing liner. We obtained early reliability data by thermally stressing bulk device. Bulk device parameters such as junction and gate leakage currents and overlap capacitance were stable after BEOL anneal stress. We also demonstrated the extendibility of Cu contact metallization using 15 nm contacts.

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria

The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.

This paper will present results obtained during the early development of a lithography process to meet the requirements of the 65 nm node in the BEOL. For the metal levels, an IBM/JSR jointly developed trench level resist was characterized and implemented. Resist image profile, process window, through pitch performance, image shortening and the effect of illumination conditions are discussed. Results from focus - exposure monitor (FEM) wafers are shown which were characterized for minimum resolution, process window and electrical continuity through a maze structure. For the via levels, results from another IBM/JSR jointly developed resist with high resolution and process windows are described. Process windows for nested and isolated vias are given, as well as results showing the improvement in process window and resolution due to the ARC etch. The results also include FEM measurements showing the electrical continuity through simple via chain structures versus the dimension of the via.

We describe an advanced 0.13 /spl mu/m CMOS technology platform optimized for density, performance, low power and analog/mixed signal applications. Up to 8 levels of copper interconnect with the industry's first true low-k dielectric (SiLK, k=2.7) (Goldblatt et al., 2000) result in superior interconnect performance at aggressive pitches. A 2.28 /spl mu/m/sup 2/ SRAM cell is manufactured with high yield by introducing elongated local interconnects on the contact level without increasing process complexity. Trench based embedded DRAM is offered for large area memory. Modular analog devices as well as passive components like resistors, MIM capacitors and intrinsic inductors are integrated.

Robust ultrathin (20 nm) trilayer low k SiNx/SiNy/SiCNH dielectric Cu caps (k ~4.0-4.2) with post ultraviolet (UV) cure compressive stress were developed and integrated into 22nm CMOS Back End Of Line (BEOL) devices. The new cap reduces device's capacitance (~ 4 %) and enhances stress stability in Cu-Ultra low k structures

We report herein the demonstration of a simple, low-cost Cu back-end-of-the-line (BEOL) dual-damascene integration using a novel photo-patternable low-κ dielectric material concept that dramatically reduces Cu BEOL integration complexity. This κ=2.7 photo-patternable low-κ material is based on the SiCOH-based material platform and has sub-200 nm resolution capability with 248 nm optical lithography. Cu/photo-patternable low-κ dual-damascene integration at 45 nm node BEOL fatwire levels has been demonstrated with very high electrical yields using the current manufacturing infrastructure. The photo-patternable low-κ concept is, therefore, a promising technology for highly efficient semiconductor Cu BEOL manufacturing.

In the present study, the electrical characteristics of metal-insulator-semiconductor capacitors with Cu and Ta electrodes on porous SiCOH dielectric subjected to bias-temperature stress (BTS) are investigated. The capacitor with Cu electrode exhibits stable capacitance-voltage (C-V) characteristics after being subjected to BTS of 0.5 MV/cm at 200°C, while Ta ions readily drift into porous SiCOH under the BTS of 0.5 MV/cm and a lower temperature at 150°C, as indicated by the observation of a larger flatband voltage shift during C-V sweep afterward. The leakage behavior of porous SiCOH is investigated using a voltage ramp method after the capacitors are subjected to BTS to study the conduction mechanism associated with the metal-ion drift into the dielectric. It appears that the leakage of capacitors with Ta electrodes starts to increase after BTS and falls into the Poole-Frenkel conduction regime, indicating that Ta ions drift into porous low-k under BTS and subsequently act as electron traps. The leakage of capacitors with Cu electrodes, however, retains almost the same characteristics as those before BTS, suggesting that the increase of leakage for capacitors with Ta electrodes is induced by the drifted Ta ions instead of the degradation of dielectric material.