Search

We present an antenna-in-package system integrated with a meander line antenna based on low temperature co-fired ceramic (LTCC) technology. The proposed system employs a meander line patch antenna, a packaging layer, and a laminated multi-chip module (MCM) for integration of integrated circuit (IC) bare chips. A microstrip feed line is used to reduce the interaction between patch and package. To decrease electromagnetic coupling, a via hole structure is designed and analyzed. The meander line antenna achieved a bandwidth of 220 MHz with the center frequency at 2.4 GHz, a maximum gain of 2.2 dB, and a radiation efficiency about 90% over its operational frequency. The whole system, with a small size of 20.2 mm×6.1 mm×2.6 mm, can be easily realized by a standard LTCC process. This antenna-in-package system integrated with a meander line antenna was fabricated and the experimental results agreed with simulations well.

This paper investigates the influence of the pulse width, pulse period, and duty ratio on the damage effect of the GaAs pseudomorphic high electron mobility transistor (PHEMT) under the injection of the repletion pulse. First, a damage model is established and verified. Then, based on this model the influence of pulse parameters on the damage effect of the GaAs PHEMT is analyzed. It can be seen that the pulse parameters can significantly affect the damage effect of the device. The increase of the pulse width can aid the damage of the device by increasing the heat of the device obtained by the signal. The influence of the pulse period depends on its variation caused by the change of the pulse width or the pulse interval. When the variation results from the change of the pulse width, the pulse period is inversely proportional to the damage time of the device. When the variation results from the change of the pulse interval, the pulse period is directly proportional to the damage time. The duty ratio is inversely proportional to the damage time of the device by affecting the heat production and dissipation simultaneously. It is found that there is a pulse period and duty ratio safe thresholds. When the injected signal is in the threshold range, the device is safe and has not potential damage under the effect of the repetition pulse.

This letter studies the effect of the thickness of the top electrode on the performance of a SiNx resistive switching layer. We fabricated six devices with Ta electrodes of different thickness values (8 nm, 10 nm, 15 nm, 30 nm, 40 nm, and 50 nm) in a Ta/SiNx/Pt structure and then systematically investigated their performance. The high electrode thickness devices show stable and self-compliant bipolar resistive switching characteristics. In contrast, low electrode thickness devices display unstable RS behavior and have a high set voltage. In the low resistance state region, the Ta/SiNx/Pt devices obey Ohmic conduction, while in the high resistance state region, the conduction mechanism is Schottky emission. To explain the different RS behavior in the two device types, a nitrogen-ion-based model has been presented. According to this model, the device with a thicker top electrode has a stronger nitrogen accommodation ability, while the migration of nitrogen ions and silicon dangling bonds dominates conductive behavior.

For the problems of the oversized voltage and undersized displacement in the electrostatic micro actuator of transverse loading recently, a silicon micro actuator model with characteristics of large-displacement and low-voltage is presented based on the principle of vertically-horizontally bending. The deflection equation of the micro actuator is derived. The axial static electricity, temperature stress and axial squeezing pressure on the deformation of micro-beam are analyzed. The simulation shows that the displacement is as big as 17.5μm when the driving voltage is as low as 5V. The displacement is much larger than the deformation of the current micro actuator.

A novel 4H-SiC MESFET with stepped-channel (stepped-spacer) structure is proposed for the first time and analyzed by 2D numerical simulation. Based on the stepped buried oxide structure of SOI which can produce additional electrical Electric field peaks, much more advantages can be obtained through a stepped-channel structure compared to that of the field terminal technology, such as an obvious increase of the breakdown voltage which is equal to the electric field to the path integral, and the lower capacitances lead to a higher cut-off frequency. The simulation results show that a 100% higher saturated drain current and a 153% larger breakdown voltage can be obtained utilizing the stepped-channel structure MESFET than those of the conventional counterpart.

4H-SiC based semicircular electrode metal-semiconductor-metal (SEMSM), triangular electrode MSM (TEMSM) and conventional electrode MSM (CEMSM) ultraviolet (UV) sensors have been modeled, investigated and characterized with numerical simulator ISE-DESSIS. By comparing with relevant experimental data, the model correctness is verified. The electrical and optical features of these sensors are simulated and calculated to character the effect of the novel electrode on performance enhancement. In contrast to CEMSM device, the SEMSM and TEMSM sensors show an outstanding superiority in terms of higher photocurrent, comparable low dark current and excellent quantum efficiency. At a bias of 30 V, the dark currents of SEMSM and TEMSM sensors are below 3.5 pA and the photocurrents are 20.7 nA and 23.7 nA under 310 nm UV illumination, respectively. Furthermore, the peak responsivity is estimated to be larger than 0.135 A/W, 0.156 A/W at 290 nm and maximum quantum efficiency at 280 nm is 58.8% and 67.7% for semicircular and triangular electrode structure, respectively.

In this paper, the positive and negative effects of oxide fixed charge on the breakdown characteristic of lateral SiC super junction devices are studied. Simulation results show that in the super junction devices with oxide layer, the negative (or positive) fixed charge on the SiO2/SiC interface act as a like p-pillar (or n-pillar) and enhance the depletion of n-pillar (or p-pillar), which result in a charge compensation and improvement of the breakdown characteristics of the devices. At the same time, a phenomenon of electric field crowding can be caused by the fixed charge and result in a decreasing of the breakdown voltage, this negative effect can be suppressed sufficiently by a field plate.

SiC MIS structure with ultra-thin Al2O3as gate dielectric deposited by Atomic Layer Deposition(ALD) on epitaxial layer of 4H-SiC(0001)80N-/N+ substrate is fabricated. The experimental results indicate that the prepared ultra Al2O3gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25MV/cm, excellent interface properties(2×1013cm-2•eV-1) and low gate-leakage current (IG=1×10-3A/㎝-2@EOX=8MV/cm). Analysis of current conduction mechanism in deposited Al2O3gate dielectric has also been systematically performed. The confirmed conduction mechanisms consisted of FP emission, FN tunneling, DT and Schottky emission. And the dominance of these current conduction mechanisms depended on applied electrical field, When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3is 1.4eV, which can meet the requirement of SiC MISFET devices.

A new asynchronous wrapper circuit is proposed based on standard cells for the realization of point to point high speed seamless data transmission. The wrapper is realized from the Signal Transition Graph (STG) by Petrify based on the fundamental GALS system structure. The asynchronous circuit includes the design of synchronous/asynchronous interface and local clock which can be suspended. The traditional EDA tools are merged together with asynchronous circuit design, and the wrapper only has standard cells but not special asynchronous logic gates. The simulation and verification were made by Modelsim and Quartus respectively, and the results have shown that the GALS system works properly and has a preferable performance.

Some new techniques include n- shielding, buried channel and field plate are firstly adopted together for design and fabrication of 4H-SiC microwave MESFETs. The testing results show that a relatively broad and uniform transconductance versus gate voltage was obtained using a 0.1m n- shielding. 0.3mm gate periphery device shows good DC and RF performance such as 5.27W/mm power density, 6.7dB power gain and 43% power added efficiency at 2.3GHz under pulse operation. Compared to conventional SiC MESFETs, a gate lag ratio as high as 0.84 can be achieved for the developed devices even under a nearly actual operating condition.

A 19 mW highly integrated GPS receiver with a ΣΔfractional-N synthesizer is presented in this paper. Fractional-N frequency synthesizer architecture was adopted in this work, to provide more degrees of freedom in the synthesizer design. A high linearity low noise amplifier (LNA) is integrated into the chip. The radio receiver chip was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process and packaged in a 48-pin 2 mm×2 mm land grid array chip scale package. The chip consumes 19 mW (LNA1 excluded) and the LNA1 6.3 mW. Measured performances are: noise figure 36 dB, and −108 dBc/Hz @ 1 MHz phase noise offset from the carrier. The carrier noise ratio (C/N) can reach 41 dB at an input power of −130 dBm. The chip operates over a temperature range of [−40, 120] °C and ±5% tolerance over the CMOS technology process.

A wide-gap thin film cathode of nanometer scale is drafted out. When an anode voltage is applied, a double-triangle barrier will be formed inside the thin film on the substrate, so that the electron emission process is similar to the tunneling in a double-barrier diode. In this paper, the electron-tunneling coefficient is calculated with a matrix approach, the emission current being integrated with the Simpson quadrature method. It is found that both the tunneling coefficient and the emission current are of resonant property. The resonant apex is sharp and the peak-to-peak value reaches six orders of magnitude (10 6 ). The resonant points that benefit the electron emission are not few. In practical situation, the applied fields may be greatly intensified by the agglomerations of the local impurities, defects and the interface states at the FEE surface; so the thickness may be well beyond the nanometer scale and the applied field intensity may be greatly reduced.

Recently, the visible light communication (VLC) based on LEDs has attracted much attention. In order to realize multi-users indoor VLC system based on the hybrid full-duplex, we design a kind of illumination/communication terminal and present the corresponding network model in this paper. We propose a multi-access scheme, which can avoid the access collision and network congestion. Meanwhile, we present a method to establish the link between users and expound the routing strategy of information forwarding. Besides, we evaluate the network performance by numerical simulations in aspects of access collision probability, throughput, access time and link establishment time. The results show that the proposed multi-access scheme and routing strategy are feasible for indoor VLC system.

A CMOS fully differential integrator based on quasi-floating gate technique is proposed. Its detailed structure, transfer characteristic and integral performance are analyzed. Using the integrator circuit, a fully balanced fifth-order Chebyshev low-pass filter, which have a 2MHz cutoff frequency and 346.1μW power dissipation, is designed by the RLC ladder simulation method. Theoretical analysis and the feasibility of the filter have been verified by the simulation results.

The large current effect of silicon germanium heterojunction bipolar transistors fabricated on thin silicon-on-insulator is included in the model. As the current is two-dimensional, the injection for large current is vertical plus horizontal and is quite different from that of the bulk device. Critical parameters modeling the large current, such as the collector injection width, the hole density and the corresponding potential in the injection region, are discussed, and the influence to the transit time is also analyzed.

A novel structure of a ZnO thin-film transistor with a double-gate and double-layer insulator is proposed to improve device performance. Compared with the conventional ZnO thin-film transistor structure, the novel thin-film transistor has a higher on-state current, steeper sub-threshold characteristics and a lower threshold voltage, owing to the double-gate and high-k dielectric. Based on two-dimensional simulation, the potential channel distribution and the reasons for the improvement in performance are investigated.