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Purpose The purpose of this paper is to develop an field programmable gate array (FPGA)-based neuron circuit to mimic dynamical behaviors of tabu learning neuron model. Design/methodology/approach Numerical investigations for the tabu learning neuron model show the coexisting behaviors of bi-stability. To reproduce the numerical results by hardware experiments, a digitally FPGA-based neuron circuit is constructed by pure floating-point operations to guarantee high computational accuracy. Based on the common floating-point operators provided by Xilinx Vivado software, the specific functions used in the neuron model are designed in hardware description language programs. Thus, by using the fourth-order Runge-Kutta algorithm and loading the specific functions orderly, the tabu learning neuron model is implemented on the Xilinx FPGA board. Findings With the variation of the activation gradient, the initial-related coexisting attractors with bi-stability are found in the tabu learning neuron model, which are experimentally demonstrated by a digitally FPGA-based neuron circuit. Originality/value Without any piecewise linear approximations, a digitally FPGA-based neuron circuit is implemented using pure floating-point operations, from which the initial conditions-related coexisting behaviors are experimentally demonstrated in the tabu learning neuron model.

Mathematical modifications have been made to the Izhikevich Neuron Model to allow for a simple, low-area digital hardware implementation with low computational intensity. The implemented neuron circuit only requires one input parameter to replicate all of the cortical neuron behaviours described by Izhikevich. The low hardware requirements of this neuron implementation make large, highly parallel digital spiking neural networks of this neuron feasible. Additionally, the model requires fewer external parameter changes to exhibit diverse neuron behaviours. The alterations made to create this novel model are presented in detail with a performance comparison to the original Izhikevich Neuron. Subsequently a digital hardware realization is presented and its performance is characterized.

We have developed a cellular neural network formed by simplified processing elements composed of thin-film transistors. First, we simplified the neuron circuit into a two-inverter two-switch circuit and the synapse device into only a transistor. Next, we composed the processing elements of thin-film transistors, which are promising for giant microelectronics applications, and formed a cellular neural network by the processing elements. Finally, we confirmed that the cellular neural network can learn multiple logics even in a small-scale neural network. Moreover, we verified that the cellular neural network can simultaneously recognize multiple simple alphabet letters. These results should serve as the theoretical bases to realize ultra-large scale integration for brain-type integrated circuits.

We present a low-power compact circuit for the event-driven readout of tactile sensors. The taxel is based on the POSFET device, a sensotronic unit where a piezo-electric material is deposited on the gate of a transistor, integrated with a Leaky-Integrate and Fire neuron circuit. This device encodes the applied force with trains of digital pulses, using the asynchronous Address Event Representation protocol. The instantaneous output spiking frequency is directly proportional to the force applied to the taxel. We show a full characterization of the device as well as quantitative measurements from a prototype fabricated on AMS CMOS 350-nm process. The taxel can reliably distinguish applied forces from 0.1 N up to 1.5 N.

The authors present a spike-triggered adaptive neuron circuit with input current modulation. Unlike adaptive neuron circuits where adaptation is realised by leakage modulation, the circuit presented in this Letter modulates the input current to membrane capacitor. Therefore, it is possible to reduce extra power consumption originating from increased leakage. Threshold voltage modulation of silicon on insulator (SOI) MOSFET by back gate effect is used to change the amount of injected current for the same input voltage. Through this method, the circuit in this work consumed 25.9% less power than the one modulating leakage.

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

Spiking neural networks (SNNs) are promising because they have the ability to represent signal strength information with a simple sequence of spikes having the same height. In this paper, we propose an RRAM-based analog neuron circuit for the weighted spiking neural network which is energy-efficient and hardware-friendly. We have designed the neuron circuit to show that the weighted spiking neural network can be implemented in analog and works properly.

International audience; CMOS neuron circuits used to implement neuromorphic chips require extensive circuitry to program the memristive cell, thus eliminating most of the density advantage gained by the adoption of memristive synapses. This paper presents a CMOS neuron circuit that provides a compact and cost-efficient programming interface in which semiconductor capacitors are replaced by a memristive device. The neuron circuit also features an adjustable firing threshold with a strict control of the power consumption during the learning process.

International audience; Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology.

Firing patterns discern the electrical activities in biological neurons when intracellular and extracellular ions are pumped into cells and exchanged there. Artificial neural circuits can be tamed to reproduce similar firing modes from biological neurons by applying appropriate physical stimuli. Photocurrent generated in the phototube can be used as a signal source, which can stimulate the neural circuits, while the involvement of which branch circuit will be much different because the channel current can control the dynamics of functional neuron to a different degree. In this paper, based on a nonlinear (FitzHugh-Nagumo, FHN) neural circuit composed of one capacitor, induction coil, nonlinear resistor, two ideal resistors and one periodical stimulus, the phototube is incorporated into different branch circuits for changing the channel current and the biophysical role of photocurrent is investigated. The dynamical equations of three types of system are unified, though they fall in different areas in parameter space. The membrane potential can be directly changed and firing modes are switched when photocurrent is activated to change the channel current by connecting the phototube to the capacitor. The induced current across the induction coil is regulated to balance the external stimulus when the phototube is connected to the induction coil in series. The two types of photosensitive neuron models constructed in this paper are compared with the photocurrent driven inductive branch showing that the photocurrent driven capacitive branch can very effectively regulate the membrane potential and greatly improve the photosensitive sensitivity.

In this paper, we propose two emulator circuits. Firstly, we present a novel memristor emulator based on operational transconductance amplifier (OTA) which is different from classical TiO2 memristor. This memristor emulator has a threshold switching mechanism. Secondly, we create a novel neuron circuit using proposed memristor, which is capable of generating spiking and bursting firing behaviors, with a biologically plausible spike shapes. The behavior of this neuron circuit can be adjusted by changing only one external biasing voltage. This neuron circuit mimics the behavior of cortical neurons, such as regular spiking (RS), intrinsic bursting (IB), chattering (CH) and fast spiking (FS). Proposed emulator circuits are compatible with VLSI systems and they can also be implemented by using discrete circuit components for different applications.

A novel leaky integrate-and-fire (LIF) neuron circuit based on the gradual switching in resistive random access memory (RRAM) device is put forward, in which threshold modulation can be achieved. Its threshold modulation and spike generating functions are verified through HSPICE simulation. In unsupervised pattern recognition for handwritten digits in MNIST dataset, its advantage in improving the accuracy (from about 70% to more than 95%) is demonstrated. Benchmarking results indicate that this novel neuron is much faster and can save about 66% area compared to one previously proposed.

We propose a simple and compact thyristor-based neuron circuit. The thyristor exhibits bi-stable characteristics that can mimic the action potential of the biological neuron, when it is switched between its OFF-state and ON-state with the help of assist circuit. In addition, a method of inter-neuron connection with synaptic devices is proposed, using double current mirror circuit. The circuit utilizes both short-term and long-term plasticity of the synaptic devices by flowing current through them and transferring it to the post-synaptic neuron. The double current mirror circuit is capable of shielding the pre-synaptic neuron from the post synapticneuron while transferring the signal through it, maintaining the synaptic conductance unaffected by the change in the input voltage of the post-synaptic neuron.

Spiking neural circuits have been designed in which the memristive synapses exhibit spike timing-dependent plasticity (STDP). STDP is a learning mechanism where synaptic weight (the strength of the connection between two neurons) depends on the timing of pre-and post-synaptic action potentials. A known capability of networks with STDP is detection of simultaneously recurring patterns within the population of afferent neurons. This work uses SPICE (simulation program with integrated circuit emphasis) to demonstrate the spatio-temporal pattern recognition (STPR) effect in networks with 25 afferent neurons. The neuron circuits are the leaky integrate-and-fire (I&F) type and implemented using extensively validated ambipolar nano-crystalline silicon (nc-Si) thin-film transistors (TFT) models. Ideal memristor synapses are driven by a nanoparticle memory thin-film transistor (np-TFT) with a short retention time attached to each neuron circuit output. This device serves to temporally modulate the conductance path from post-synaptic neurons, providing rate-based and timing-dependent learning. With this configuration, the use of a crossbar structures would also be possible, providing dense synaptic connections and potentially reduced energy consumption.

In this paper, a ring-oscillator (RO) based sub-1V leaky integrate-and-fire (I&F) neuron circuit is proposed, that can support user programmable refractory period and spike-frequency adaptation. Designed in CMOS 65-nm TSMC process, the neuron can operate from 0.9 V and has the unique feature that the same circuit can be programmed to operate either at biological time-scales or at accelerated time-scales. As ring-oscillators in nanometer CMOS are small compared to capacitors used in existing I&F silicon neuron (SiN), a large number of RO-based neurons can be integrated along with complex digital circuits to realize a single-chip Neuromorphic-SoC.

We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has shortterm and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (IF i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

In this paper, a modified spiking neuron circuit (MSNC) with memory threshold is presented. The MSNC can store the potential of the threshold signal at the latest firing time as threshold under the control of pulse, implying the memory of threshold. We extend the definition of the least common multiple to obtain the iterative map of firing phase of the MSNC. By studying the iterative map of firing time and firing phase, the characteristics of dynamics and statistics, including chaos and pseudo randomness, are revealed. Accordingly, the chaotic map generated by MSNC is applied to image encryption. The resulting image is totally noise-like. Furthermore, the hardware circuit of MSNC is done in our laboratory. Through experiment simulation and actual circuit testing, the results verify the design.

Neuron is the basic entity that transmits and process information through generated action potential or spikes in neuromorphic systems. In real scenario there is no fixed threshold in the cortical neuron but it varies for every neuron. In this work, the neuron with threshold modulation capability is implemented in analog VLSI using CMOS technology. The proposed neuron circuit generated time varying threshold voltage that applies to neuron input. The circuit is capable of generating a variety of different spiking patterns with diversity similar to that of real biological neuron cell. The paper describes how threshold modulation is achieved besides operation of the circuit. Simulation results of different patterns are presented along with threshold modulation to the circuit as well as power analysis for each pattern. The circuit is implemented in 0.18µm technology in Cadence Design Environment. The neuron circuit is efficient to be used in microcircuits as it consumes low power.

We present an analog neuron circuit consisting of a small number of metal-oxide semiconductor (MOS) devices operating in their subthreshold region. The dynamics of the circuit were designed to be equivalent to the well-known Volterra system to facilitate developing the circuit for a particular application. We show that a simple nonlinear transformation of system variables in the Volterra system enables designing a neuron-like oscillator, which can produce sequences in time of identically shaped pulses (spikes) by using current-mode subthreshold MOS circuits. We present experimental results of the fabricated neuron circuits as well as an application in an inhibitory neural network, where the neurons compete with each other in the frequency and time domains.

Artificial neural networks have the potential for parallel processing with integrated circuit technology. Over 1 million gates are now available in the latest FPGA (Field Programmable Gate Array). However, the sum-of-product circuit used for evaluating inputs of the neuron model is complex and not effective for hardware implementation by FPGAs. In this paper, an improved calculation algorithm of the perceptron-type neuron model is proposed, based on multidimensional binary search. Since the search does not need the sum-of-product circuit, the designed neuron circuit is small and fast. It is suitable for hardware implementation. © 2001 Scripta Technica, Electr Eng Jpn, 138(2): 24–32, 2002

A modified pulse-coupled spiking neuron circuit (MPSNC) with memory threshold is presented. It is constructed with two single modified spiking neuron circuits (MSNCs). In MPSNC, one MSNC stores the potential of its threshold signal at the latest firing time of another MSNC as threshold, implying a short-term cross memory. We extend the definition of least common multiple to obtain the firing phase of MPSNC. By studying the iterative map of firing time and firing phase, the dynamics and statistics are revealed. The chaotic map of firing phase is applied to image encryption. Besides, the hardware circuit and simulation are built.

A compact architecture for pulse-coupled neuron circuit is demonstrated by fabrication and characterization of an analog CMOS circuit, in which a multipath-switching device is integrated with a feedback loop of the CMOS inverter chain. The synaptic weights are obtained by the combination of different channel width of multipath- switching device using temporal codes of pulse-width modulation. Experimental results show that the output pulse stream of neuron circuit carries the weight information on the pulse frequency.

A current-mode MOS neuron circuit with 4-bit programmable weights is presented by using CMOS technology. The weights of the neuron have high resolution and also can easily be digitally stored. The resolution can be extended into high levels such as 8-bit, etc. by the design methodology presented in this paper. The operational principle of the neuron is discussed. Circuit simulation has been made by use of SPICE II. The results give a good agreement for the design requirements.

By using the Field Programmable Analog Array (FPAA) IC with embedded switched capacitor techniques, the circuit design for a neuron is proposed. First, the FPAA IC and EDA software platform are introduced. Second, the architecture and working principle of the FPAA neuron circuit are present. Third, by using the FPAA EDA software and hardware developing platform, the FPAA neuron circuit has been designed and tested.

The artificial neuron or information-processing cell was designed primarily as a component for experimental neuron-network studies. With minor additions, it could be used for perceptron-type experiments. Each cell has ten exciting and ten inhibiting inputs, and each input has a separate weight associated with it. The operation of the cell depends upon the difference, between the weighted sums of the exciting and the inhibiting input signals.

We present in this paper an electronic circuit implemented in Austria Microsystems (AMS) 0.35 mm CMOS technology for a neuron cell part of the multi-nested"" neuron family of the Cellular Neural Network (CNNs). The CMOS universal neuron circuit has three inputs and two nests. Static and dynamic SPICE simulation results are shown and verify the model and functional capabilities of a universal CNN neuron cell described in a companion paper by R. Dogaru et al. (2003).""

We present a low-power analog circuit for implementing a model of a leaky integrate and fire neuron. Next to being optimized for low-power consumption, the proposed circuit includes elements for implementing spike frequency adaptation, for setting an arbitrary refractory period and for modulating the neuron's threshold voltage. We present experimental data from a prototype chip, implemented using a standard 1.5 /spl mu/m CMOS process.

An expandable on-chip learning neural network chip with 8-neuron and 64-synapse is designed and fabricated with a standard 0.6 /spl mu/m CMOS technology. Large-scale neural network with arbitrary layers can be constructed by connecting unit chips. A novel neuron circuit with programmable parameters is proposed. It generates riot only the sigmoid function but also its derivative. The neuron has a push-pull output stage to gain strong driving ability in both charge and discharge processes, which is very important in heavy load situations. An improved Gilbert multiplier is also proposed. It has one end current output and precise zero point. The learning system itself can be used as a refresh tool to keep the weight value right. Experiment results show that it has good performance.

Fabrications and characterizations of high electron-mobility transistors (HEMTs) with a ferroelectric gate (F-HEMTs) are presented. The F-HEMT is a memory device whose threshold voltage can be changed even after it is fabricated, by using remanent polarization of the ferroelectric gate. Furthermore, the F-HEMT is promising of neural network applications, because it can act as a high-speed analog memory which stores synaptic weights in a neuron circuit. From I/sub D/-V/sub G/ characteristic measurements of F-HEMTs, it is demonstrated that the threshold voltage is shifted by 0.3 V by remanent polarization. The result indicates that F-HEMTs are sufficiently applicable for the high-speed analog memory.

A compact architecture for analog CMOS VLSI implementation of voltage-mode pulse-coupled neural network (PCNN) is presented. The main feature of the proposed neuron circuit is that the structure is compact, yet exhibiting all the basic properties of natural biological neurons. Another unique feature of the proposed neuron cell is that one node serves as both input and output, mimicking a natural biological neuron, and the neuron cell uses frequency modulated bidirectional pulse-streams. Functionality of the proposed PCNN circuit is verified with SPICE simulations.

A novel CMOS synapses circuit for using in neuron circuit is presented. The proposed new type CMOS synapses circuit with the accurate weights is composed with the CMOS inverters which have resistors inserted inside. A design of the neural-based A/D converter using the proposed CMOS synapses circuit is also presented to show a practical application.

The adaptive-learning function was successfully demonstrated in a neuron circuit using a metal/ferroelectric/semiconductor field effect transistor (MFSFET). The polarization direction of the ferroelectric gate film (SrBi2Ta2O9) of MFSFET was gradually reversed by applying a number of input pulses with a sufficiently short duration of 20 ns. Consequently, the S-D (source-drain) resistance of MFSFET was gradually changed, and the output pulse frequency of the neuron circuit was modulated by the number of input pulses.

A basic optoelectronic circuit of an artificial synaptic connection was fabricated in which analogue weights were varied electrically. Circuit simplicity and low current level operation, necessary for a large scale OEIC, were realised.

A basic optoelectronic circuit of an artificial neuron was realised in which synaptic weights were varied electrically. A primitive content addressable memory was constructed using an optical interconnection. The experimental results showed the feasibility of large-scale networks and a one-chip OEIC.