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This paper presents a fractional- N all-digital phase-locked loop (ADPLL). A 4-bit multi-delay line time-to-digital converter (MDL-TDC) using path selection technique is proposed to achieve a 4-ps resolution with 0.24-mW power consumption at 52 MS/s. A TDC offset calibration method is used to eliminate TDC metastability. An isolated constant-slope digital-to-time converter (ICS-DTC) is utilized to cancel the quantization noise (Q-noise) and achieve true-fractional delay. By tuning DTC compensation, spur and Q-noise are suppressed by 14 dB. To speed up the locking process of the ADPLL, a counter-based coarse PLL is integrated to monitor and compensate for large frequency and phase jump while consuming almost zero power. The proposed ADPLL is implemented in a 40-nm standard CMOS process, occupying a silicon area of 0.36 mm2. When TDC offset calibration is turned on, the in-band noise is suppressed by 20 dB. The measured results show 0.78-ps rms jitter and −40-dBc in-band fractional spur are achieved, corresponding to a figure of merit (FOM) of −235 dB. [ABSTRACT FROM AUTHOR]

This article proposes a fractional- N charge pump phase-locked loop (C P-PLL) with fast two-point modulation calibration using Duty-Cycle and Polarity Tracking technique. The proposed calibration method can perform delay and gain calibration within 15 μs, respectively. A DTC-assisted Polarity Detector is used to track and countervail the propagation delay of two modulation paths. A TDC-based Duty-Cycle Detector is used to monitor and compensate the two paths gain mismatch. By comparing the code with the threshold set in the look-up table (LUT), a quick calibration can be achieved. To maintain high out-band phase noise performance and stronger robustness, a Class-C oscillator using Capacitance Desensitization technique and Cross-Bias technique is adopted in the design. The proposed C P-PLL is implemented in a standard 110-nm CMOS technology, occupying 2.7 mm2 silicon area. The post-simulation results show the proposed calibration method can calibrate the delay/gain mismatch within 30 μs. Fast calibration mode supports calibration time within 62.5 ns. The phase noise performance is −91-dBc/Hz@100 kHz, −119-dBc/Hz@1 MHz. The entire C P-PLL dissipates 20.9-mW and achieves an RMS jitter of 6.2 ps, corresponding to a figure of merit (FOM) of −211-dB. [ABSTRACT FROM AUTHOR]