Search

This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps. [ABSTRACT FROM AUTHOR]

A physical design methodology is presented to synchronize digital application specific integrated circuit (ASIC) designs by a resonant rotary clock network. One novelty of the proposed RotaSYN flow is that the ASIC products of RotaSYN can operate at previously unattainable (relatively) low-frequency ranges of hundreds of megahertz. The dynamic resonant frequency divider is used to implement the low-frequency operation; and low in comparison to the norm of gigahertz-range of operation for resonant clocking reported in this paper. In SPICE-based simulations, the efficacy of the proposed flow and novel algorithms in RotaSYN is demonstrated using performance metrics of the wirelength, skew, and power on international symposium on physical design-10 clock benchmark circuits. In addition, RotaSYN is compared to three publicly available industrial designs that include the ARM Cortex M0 against equivalent clocks generated with a traditional phase locked loop (PLL) and distributed with an industrial clock tree synthesis tool flow. The RotaSYN methodology is implemented at three different target frequencies of 880 MHz, 500 MHz, and 220 MHz for the industrial designs. SPICE simulations show an average of 29% power savings for the industrial designs overall, solely thanks to 66% power savings on the clock generation and distribution networks, operating at a frequency of 880 MHz on comparison to the PLL-based design with a clock tree synthesized with an industrial EDA tool. [ABSTRACT FROM AUTHOR]