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An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM. [ABSTRACT FROM AUTHOR]

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM. [ABSTRACT FROM AUTHOR]

Summary: This work presents a macro modeling approach for the time‐mode cyclic ADC. The proposed ADC macro model is realized using the time‐to‐voltage converter (TVC) and the voltage‐to‐time converter (VTC) that are the key building blocks of time‐mode ADCs. In addition, the effect of circuit nonidealities and error sources of the time‐mode ADC including parasitic capacitance, current source output resistance, switch on‐resistance, capacitor mismatch, and comparator offset are incorporated in the macro model. The simulation time of the proposed ADC macro model showed 87.1% reduction compared to the all transistor level ADC circuit. As a result, the proposed ADC macro model can facilitate the ADC design and leverage the ADC nonideality analysis. Furthermore, the proposed macro model can be used for ADC calibration scheme development. As a practical design example, the macro model for an 8‐bit time‐mode cyclic ADC has been realized, where the nonideality analysis, design optimization, and calibration scheme development based on the proposed macro model have been demonstrated. [ABSTRACT FROM AUTHOR]

Purpose: Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach: A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET's and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings: The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value: The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as "spider-latch". [ABSTRACT FROM AUTHOR]

An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator. [ABSTRACT FROM AUTHOR]

In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated. [ABSTRACT FROM AUTHOR]

Abstract This paper configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100% energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N -bit SAR ADC shows a 50% capacitor area reduction in comparison with the conventional SAR ADC. [ABSTRACT FROM AUTHOR]

Abstract A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC. [ABSTRACT FROM AUTHOR]

A signal-dependent dithering calibration exploiting noise quantiser (NQ) technique to correct capacitor mismatch and inter-stage gain error in pipelined successive approximation register (SAR) ADCs is proposed. With signal-dependent dithering injection, capacitor mismatch and gain error are extracted and subsequently calibrated as one error in the background. Besides, a novel NQ is proposed for a dithering injection only when the residue is near the threshold of the comparator, thereby allowing the injection of dithering without consuming the dynamic range. The simulation results show that the calibration can significantly improve the performance of pipelined SAR ADCs without extra hardware overhead and timing budget. [ABSTRACT FROM AUTHOR]

In this paper, two essential components of the Flash ADC are designed and integrated within a new Flash ADC architecture. The power consumption is reduced by realizing a switched-capacitor positive feedback (SCPF) comparators structure as a replacement for conventional comparators structure. The SCPF comparator is tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision. Furthermore, the encoding stage is implemented using N parallel independent components of one single AND gate each, where N is the number of quantized regions. This structure provides fast encoding with minimal encoding activities. The design architecture exploits two stages, which are separated by latches. The first stage allocates the analog input to a quantized region, while the second stage converts the level of the quantized region into its corresponding binary code. This separation is considered the key success for incorporating the SCPF comparators structure into our Flash ADC architecture. HSPICE simulations of the proposed design use 35 nm Synopsys FinFet technology and 1-V power supply. The simulation results show that our 5-bit Flash ADC can function at a sampling frequency of up to 1 GHz, with an input signal of 500 MHz at Nyquist rate, where the amplitude input signal is ranging from 0.2 to 0.8 V with an overall maximum power consumption of 3 mW. [ABSTRACT FROM AUTHOR]

This paper presents a capacitor sample-hold oscillator architecture which realizes temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. Due to its dual-way charging and discharging structure, the peak charge voltage for each phase will eventually stabilized around half the supply voltage. The frequency of the oscillator depends on the RC time constants of capacitors charging (discharging) across passively-temperature-stabilized resistive elements and the comparator delay time. By analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents to achieve temperature stabilization of the delay time, this architecture improves the overall temperature stability. This architecture has been designed and verified in 0.18-μm CMOS technology. The simulation results demonstrate this design consumes 7.99 μW from a 1.8 V supply voltage at 58.9 kHz and achieves a temperature stability of best 22.19 ppm/℃(TT Corner) from −40◦C to 90◦C, and frequency variations of ± 0.3 % for supply changes from 1.25 to 1.8 V. [ABSTRACT FROM AUTHOR]

Charge scaling data converters include a binary-weighted capacitor array in their structure. New methods for the placement and sizing of capacitor arrays with increased ratio accuracy and improved converter linearity are presented in this paper. A new model of statistical variation is used, which takes into account both spatial correlation between devices and device area. This is combined with a novel analytical model for the linearity metrics of a charge scaling digital-to-analog converter. Minimizing the variance of the linearity metrics directs a new chessboard placement method for the capacitor array. Chessboard placement is shown to be superior to the state of the art in consideration of both random and systematic mismatch. The new analytical model is then used to develop a flow for capacitor array sizing. [ABSTRACT FROM PUBLISHER]

The propagation of Analog Single Event Transients (ASETs) to multiple outputs of Bipolar Junction Transistor (BJTs) Integrated Circuits (ICs) is reported for the first time. The results demonstrate that ASETs can appear at several outputs of a BJT amplifier or comparator as a result of a single ion or single laser pulse strike at a single physical location on the chip of a large-scale integrated BJT analog circuit. This is independent of interconnect cross-talk or charge-sharing effects. Laser experiments, together with SPICE simulations and analysis of the ASET’s propagation in the s-domain are used to explain how multiple-output transients (MOTs) are generated and propagate in the device. This study demonstrates that both the charge collection associated with an ASET and the ASET’s shape, commonly used to characterize the propagation of SETs in devices and systems, are unable to explain quantitatively how MOTs propagate through an integrated analog circuit. The analysis methodology adopted here involves combining the Fourier transform of the propagating signal and the current-source transfer function in the s-domain. This approach reveals the mechanisms involved in the transient signal propagation from its point of generation to one or more outputs without the signal following a continuous interconnect path. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive investigation of several important error sources for the successive-approximation register (SAR) analog-to-digital converters (ADCs). The error sources that we discuss in this paper include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential nonlinearities (INL/DNL) of SAR ADCs that are resulted from these error sources are analyzed and addressed. A diagnostic procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also offered and recommended in this paper. [ABSTRACT FROM AUTHOR]

A new current-comparator-based dual-channel calibration system for AC currents and AC voltages in the millivolt range has been developed. The range of generated currents is 1 mA–5 A, and the range of generated voltages is 1–500 mV. The calibration system in-phase and quadrature expanded measurement uncertainties ( $k=2$ ) are within 25\cdot 10^{\mathrm {\mathbf {-6}}} . Although the system has been developed primarily for operation at power frequencies, it is also capable of operating at frequencies up to 1000 Hz with slightly increased uncertainties. The traceability to SI units is established through the calibration of AC voltage by means of AC/DC transfer and DC voltage reference, standard resistor, capacitor, and current comparator ratios. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a rail-to-rail 460-kS/s 10-bit successive approximation register analog-to-digital converter (ADC) for the power-efficient capacitance measurement. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor capacitance-to-voltage (C2V) converter. To be compatible to the output of C2V, a bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is implemented by a single-ended cascaded binary-weighted capacitive digital-to-analog converter (DAC). The total area of the DAC array is not only limited by the matching behavior but also by the noise performance of C2V. To relax the settling requirement and improve the power efficiency, self-timing technique is employed which borrows extra half clock period for open-loop settling of preamps. The balance between noise and power consumption of dynamic comparator with preamps is also considered. The ADC circuit was implemented in 0.18- \mu m CMOS technology and occupies an active area of 0.18 \mathrm{mm}^{2} . The tested prototype achieves a signal-to-noise-plus-distortion ratio of 54 dB and a spurious-free dynamic range of 68 dB. The integral nonlinearity and differential nonlinearity are 0.5 and 0.34 least-significant-bit, respectively. The total power consumption is 21 \mu $ W corresponding to 110 fJ/conversion-step figure of merit. [ABSTRACT FROM PUBLISHER]

A preamplifier for comparators of precision low-power consumption analog-digital converters is presented. In order to lower the average consumption current of amplifier cascades, the capacitors, which fulfill the function of current sources during charging at the comparison stage, are used in them as the dynamic load. A correction circuit of the zero bias error for amplifiers of this type is developed. Modeling of the device using CMOS elements with a design rule of 0.35 μm from library XA035 of factory XFAB showed that the average current consumption at an operating frequency of 1 MHz is about 7 μA. [ABSTRACT FROM AUTHOR]

This paper presents two circuits that allow us to accurately detect either the inductor current zero crossing, or the continuous/discontinous conduction modes boundary in the switched-mode dc-dc converters. Achieved detection accuracy allows us to improve the control and efficiency of the integrated high-output current converters, i.e., converters with low-resistance power switches. Detection is based on the voltage zero-cross detector, which provides ideally zero input-referred offset and very fast results. The concept of voltage polarity detector is based on the association of a dynamic current mirror and a simple autozero comparator. This paper describes the main concept of both circuits, aspects of the design allowing us to achieve high accuracy, and presents obtained results. Circuits' performances are demonstrated on the integrated step-down dc-dc converter with IOUT = 2.5 A 30-mΩ NMOS power stage. Measured accuracy of the detection is in order of <;15 mA. [ABSTRACT FROM AUTHOR]

Abstract: A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, CMOS technology and the Pelgrom's mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology. [Copyright &y& Elsevier]

An improved power standard derived from a current comparator power bridge for calibrating active/reactive power and energy meters under sinusoidal conditions is described. Measurements can be made at any power factor from zero lag through unity to zero lead, at positive or negative power, at 120 V, 5 A, and 50 or 60 Hz. The improved power standard has an estimated uncertainty of not more than 2.5 \mu\W/VA at k = 1. Special high-accuracy current and voltage range extenders have been incorporated to extend the current and voltage ranges up to 200 A and 1200 V, respectively. [ABSTRACT FROM PUBLISHER]

A switch controlled fourth-order dual-band bandpass delta-sigma modulator (BPDSM) is proposed. It consists of two stage second-order resonator, high-speed comparator, multifeedback current digital-to-analog converter, and clock distributer. The band selection is controlled by capacitor bank, and fine frequency tuning is done by varactor. The implemented BPDSM shows a peak signal-to-noise-ratio is 41.6 dB, 42.5 dB, an error vector magnitude is 3.06%, 2.4% in 882 MHz, 955 MHz, respectively, and a differential output voltage swing is 1.32Vp-p with dc power consumption of 389 mW. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2784-2787, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27207 [ABSTRACT FROM AUTHOR]

In tills paper a second-order low distortion Sigma-Delta Modulator (EAM) with utilization of Comparator-Based Switched-Capacitor (CBSC)-based IIR filter, is explored. The advantages of this new structure are justified by the reduction of power and area. For this purpose IIR filter block can be made with single CBSC gain stage that has the same accuracy and performance of second-order filter with two Op-amps. The design of CBSC gain stages is intended to minimize the power consumption, and maximize Modulator performance. As shown in the simulation result, for a 20-KHz signal bandwidth, the modulator achieves a dynamic range of 70.2 dB and a peak signal-to-noise and distortion ratio (SNDR) of 68 dB with an over-sampling ratio of 64. In addition it consumes only 198/xW from a 1.8-V power supply at 2.56 MS/s. [ABSTRACT FROM AUTHOR]

Abstract: This paper will demonstrate how signals from analog sensors can be directly interfaced to any digital embedded system even though they may not be equipped with an on-chip ADC (Analog-to-Digital Converter), comparator or OP amp (Operational Amplifier). With only two resistors and one capacitor, we will present a solution that allows analog voltages to be measured directly using only a few digital I/O-pins. The digital target system requirements are minimized and limited to only two digital I/O-pins (with tri-state capability). No ADC, comparators, timers or capture modules are necessary. The extremely modest hardware requirements make it a suitable solution also for CPLDs/FPGAs (Complex Programmable Logic devices/Field Programmable Gate Arrays). Since this solution will allow even the simplest embedded system to be interfaced to analog voltage sensors, it has the potential of reducing design costs considerably. The proposed design is for DC or low-frequency signals and compared to other similar solution, this design needs no embedded analog blocks at all. [Copyright &y& Elsevier]

Abstract: A charge-pump and comparator based technique is presented for power-efficient pipelined analog-to-digital conversion. The technique takes advantage of a passive charge pump to implement the core function of residue voltage amplification and exploits a comparator-controlled charging circuit to buffer the residue voltage to the next stage. Unlike the conventional buffer circuit using source followers, no voltage headroom is sacrificed in this voltage buffering scheme. The comparator overshoot due to comparator delay is minimized by a self-cancellation scheme. The proposed pipelined ADC technique uses only capacitors, comparators and current sources with digital calibration to achieve low power consumption. Designed and fabricated in a 0.18μm CMOS technology, a proof-of-concept ADC has measured 39.1dB SNDR (6.2-bit ENOB) at 25MS/s while consuming 3.5mW from a 1.8V supply. [Copyright &y& Elsevier]

The Korea Research Institute of Standards and Science (KRISS) has established a reference 400-kV capacitive voltage divider for the purpose of calibrating industrial high-voltage measuring systems on site. In order to confirm the performance characteristics of the divider, a comparison of the calibration systems between KRISS and National Research Council Canada with the divider used as the transfer standard was conducted. This paper presents the comparison results and its analysis in obtaining the voltage-dependent performance characteristics of the reference 400-kV voltage divider over its entire range. [ABSTRACT FROM AUTHOR]

A modified technique for calibrating both the capacitance-ratio and dissipation-factor (DF) dials of a current-comparator-based high-voltage capacitance bridge has been developed at the Korea Research Institute of Standards and Science (KRISS). The capacitance-ratio and DF dials are calibrated in the ratio range from 1/1 to 1000/1 and in the DF range from 10 \times 10^-6 to 1 \times 10^-1 for both positive and negative polarities. From the calculated and measured values of the corresponding dial balanced readings, the errors in the capacitance-ratio- and DF-dial readings are derived. The relative uncertainty of the modified calibration technique is also obtained to be not more than 10 \times 10^-6 of unity for the ratio-dial calibration, whereas the relative uncertainty of the DF dials from 1 \times 10^-3 to 1 \times 10^-1 is not more than 0.4% of the dial indication except the dissipation lower than 1 \times 10^-3 for which the corresponding absolute uncertainty is 5 \times 10^-6. The comparison results of the calibration performed at KRISS and the National Research Council of Canada show a good consistency with the measurement uncertainty. [ABSTRACT FROM AUTHOR]

Abstract: The quantum Hall effect (QHE) discovery has revolutionized metrology by providing with a representation of the unit of resistance, , that can be reproduced within a relative uncertainty of one part in 109 and is theoretically only linked to Planckʼs constant h and the electron charge e. This breakthrough also results from the development of resistance comparison bridges using cryogenic current comparator (CCC). The QHE experimental know-how now allows the realization of perfectly quantized Quantum Hall Array Resistance Standards (QHARS) by combining a large number of single Hall bars. In the context of an evolution of the Système International (SI) of units by fixing some fundamental constants of physics, the determination of the von Klitzing constant through the use of the so-called Thompson–Lampard calculable capacitor and the realization of refined universality tests of the QHE are of prime importance. Finally, the fascinating graphene material might be a new turning point in resistance metrology. [Copyright &y& Elsevier]

A method for improving the sensitivity (or speed) of a master–slave emitter-coupled logic comparator using emitter degeneration resistors is presented. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the InP/GaInAs heterojunction bipolar transistor technology and were tested at a clock rate of 20 GHz. The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low-sensitivity value of 10 mV was obtained. [ABSTRACT FROM AUTHOR]

A radiation-hardened-by-design (RHBD) technique is described for reducing errors due to single-event effects at the floating input nodes of a switched-capacitor comparator. The technique is shown to significantly outperform the alternative ldquobrute forcerdquo design choice of increasing capacitor size. [ABSTRACT FROM PUBLISHER]

A counteracting dither technique is proposed to remedy the bit-weight error issue in pipeline analogue-to-digital converters (ADCs). A capacitor is added to the traditional comparator dither scheme. By switching the added capacitor, the residue swing increment due to comparator dither is counteracted, thereby greatly relaxing the design requirement of the residue amplifier. Behaviour-level simulation results show that the spurious-free-dynamic-range and the signal-tonoise- and-distortion-ratio are improved from 59 and 52.8 dB to 102.7 and 85 dB after calibration in a 14-bit ADC, respectively. [ABSTRACT FROM AUTHOR]

This paper presents the development of a 10 bit very low-power CMOS SAR-ADC to be used in medical implants. The first part discusses the principle schematic and the requirements for component matching and the comparator of the ADC. Additionally, the measurement results of a fabricated test chip will be given. The second part of this paper discusses the possibility of direct on-chip implementation of a capacitive pressure sensor in a switched-capacitor SAR-ADC. [ABSTRACT FROM AUTHOR]

Presents a mathematical analysis on obtaining ratio of time-varying voltages of radio meters for process instrumentation. Illustration of the block diagram; Construction of comparator circuits; Increase in voltage across charging condensers.

A simple and highly efficient successive-approximation registers (SAR) ADC realisation is proposed. It requires an opamp, a comparator and only three equal-valued capacitors. The proposed scheme is insensitive to the capacitor parasitics, and has a small capacitance spread. With an oversampled scheme, it also allows noise-shaping the remaining quantisation error. It is well-suited for low-frequency instrumentation and measurement applications, and for use in extended-counting ADCs. [ABSTRACT FROM AUTHOR]

A CMOS relaxation oscillator which generates quadrature triangular and square waveforms is presented and fabricated in 0.18 µm CMOS. The proposed oscillator consists of cascaded two-stage charge-discharge full-differential circuits with sequential common-mode comparators based on cross-coupled connection. Experimental results show that the proposed oscillator generates quadrature-phase waveforms with less than 1% phase mismatch. The proposed oscillator also achieves a tuning range of more than 40% with digitally programmable timing capacitors and offers phase noise of -132 dBc/Hz at 1 MHz offset frequency. [ABSTRACT FROM AUTHOR]