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This paper presents a high-power-density high-power-factor GaN-based two-stage electrolytic-free offline LED driver. The LED driver achieves high power density through the use of a hybrid film–ceramic stacked switched capacitor (SSC) energy buffer, and a comprehensive optimization methodology that evaluates various converter topologies and designs and minimizes overall system volume while maintaining high efficiency. Based on this optimization approach, a totem-pole bridgeless boost power factor correction (PFC) converter is selected for the first stage, while a stacked-input isolated LLC dc–dc converter is selected for the second stage. The optimization procedure also minimizes the passive volume of the SSC energy buffer incorporating the volumetric energy density of commercially available capacitors. The optimized SSC energy buffer utilized in the proposed LED driver has 50% less passive volume than a capacitor-only solution. A 600-W prototype LED driver designed using the proposed approach for universal input voltage ${{(90}}-{ 305 \ \text{V}}_{{\text{rms}}})$ and 24-V output voltage is built and tested. The PFC stage achieves a peak efficiency of 98% while the LLC stage achieves a peak efficiency of 95%. The prototyped LED driver achieves a power density of 28 W/in3. [ABSTRACT FROM AUTHOR]

Multistage matching networks are often utilized to provide voltage or current gains in resonant conversion applications, such as large conversion ratio power converters and wireless power transfer. In the conventional approach, each stage of a multistage matching network is designed to have a purely resistive input impedance and assumed to be loaded by a purely resistive load. This paper introduces an improved design optimization approach for multistage matching networks comprising L-section stages. The proposed design optimization approach explores the possibility of improvement in efficiency of the network by allowing the L-section stages to have complex input and load impedances. A new analytical framework is developed to determine the effective transformation ratio and efficiency of each stage for the case when input and load impedances may be complex. The method of Lagrange multipliers is used to determine the gain and impedance characteristics of each stage in the matching network that maximize overall efficiency. Compared with the conventional design approach for matching networks, the proposed approach achieves higher efficiency, resulting in loss reduction of up to 35% for a three-stage L-section matching network. The theoretical predictions are validated experimentally using a three-stage matching network designed for 1 MHz and 100 W operation. [ABSTRACT FROM PUBLISHER]

The recently proposed stacked switched capacitor (SSC) energy buffer architecture can extend the lifetime of single-phase ac–dc converters by replacing the electrolytic capacitors needed for twice-line-frequency energy storage with film or ceramic capacitors, while maintaining comparable effective energy density. This paper presents a methodology for further increasing the effective energy density of SSC energy buffers by optimizing the capacitance ratios of the capacitors used in the energy buffer. It is systematically shown that the relative enhancement in effective energy density depends on the required ripple ratio and the number of backbone and supporting capacitors in the energy buffer. The proposed approach can substantially increase the effective energy density of the energy buffer. For example, the effective energy density of a 1-10 enhanced unipolar SSC energy buffer, designed for a 10% ripple ratio, can be increased by 100% as a result of this capacitance ratio optimization. The presented methodology is validated using a 1-2 enhanced unipolar SSC energy buffer designed for an 8-W offline LED driver. [ABSTRACT FROM AUTHOR]

This paper introduces a MultiTrack power conversion architecture that represents a new way of combining switched-capacitor circuits and magnetics. The MultiTrack architecture takes advantages of the distributed power processing concept and a hybrid switched-capacitor/magnetics circuit structure. It reduces the voltage ratings on devices, reduces the voltage regulation stress of the system, improves the component utilization, and reduces the sizes of passive components. This architecture is suitable to dc–dc and grid-interface applications that require both isolation and wide voltage conversion range. An 18–80 V input, 5 V, 15 A output, 800 kHz, 0.93 in $^2$ (1/16 brick equivalent) isolated dc–dc converter has been built and tested to verify the effectiveness of this architecture. By employing the MultiTrack architecture, utilizing GaN switches, and operating at higher frequencies, the prototype converter achieves a power density of 457.3 W/in$^3$ and a peak efficiency of 91.3%. Its power density is 3$\times$ higher than the state-of-the-art commercial converters with comparable efficiency across the wide operation range. [ABSTRACT FROM AUTHOR]

Microinverters operating into the single-phase grid from solar photovoltaic (PV) panels or other low-voltage sources must buffer the twice-line-frequency variations between the energy sourced by the PV panel and that required for the grid. Moreover, in addition to operating over wide average power ranges, they inherently operate over a wide range of voltage conversion ratios as the line voltage traverses a cycle. These factors make the design of microinverters challenging. This paper presents a multilevel energy buffer and voltage modulator (MEB) that significantly reduces the range of voltage conversion ratios that the dc-ac converter portion of the microinverter must operate over by stepping its effective input voltage in pace with the line voltage. The MEB partially replaces the original bulk input capacitor, and functions as an active energy buffer to reduce the total size of the twice-line-frequency energy buffering capacitance. The small additional loss of the MEB can be compensated by the improved efficiency of the dc-ac converter stage, leading to a higher overall system efficiency. The MEB architecture can be implemented in a variety of manners, allowing different design tradeoffs to be made. A prototype microinverter incorporating an MEB, designed for 27 to 38 V dc input voltage, 230-V rms ac output voltage, and rated for a line cycle average power of 70 W, has been built and tested in a grid-connected mode. It is shown that the MEB can successfully enhance the performance of a single-phase grid-interfaced microinverter by increasing its efficiency and reducing the total size of the twice-line-frequency energy buffering capacitance. [ABSTRACT FROM AUTHOR]

This paper presents a new topology for a high-efficiency dc/dc resonant power converter that utilizes a resistance compression network (RCN) to provide simultaneous zero-voltage switching and near-zero-current switching across a wide range of input voltage, output voltage, and power levels. The RCN maintains desired current waveforms over a wide range of voltage operating conditions. The use of ON/OFF control in conjunction with narrowband frequency control enables high efficiency to be maintained across a wide range of power levels. The converter implementation provides galvanic isolation and enables large (greater than 1:10) voltage conversion ratios, making the system suitable for large step-up conversion in applications such as distributed photovoltaic converters. Experimental results from a 200-W prototype operating at 500 kHz show that over 95% efficiency is maintained across an input voltage range of 25-40 V with an output voltage of 400 V. It is also shown that the converter operates very efficiently over a wide output voltage range of 250-400 V, and a wide output power range of 20-200 W. These experimental results demonstrate the effectiveness of the proposed design. [ABSTRACT FROM AUTHOR]

The stacked switched capacitor (SSC) energy buffer is a recently proposed architecture for buffering energy between single-phase alternating and direct current. When used with film capacitors, it can increase the life of grid-interfaced power converters by eliminating limited-life electrolytic capacitors while maintaining comparable energy density. This paper introduces an enhanced version of the bipolar SSC energy buffer that achieves higher effective energy density and round-trip efficiency while maintaining the same bus voltage ripple ratio as the original design. Furthermore, the enhanced buffer uses fewer capacitors and switches than the original design. The enhancement in performance is achieved by modifying the control and switching patterns of the buffer switches. A prototype enhanced SSC energy buffer, designed for a 320-V bus and a 135-W load, has been built and tested. The design methodology and experimental results for the enhanced SSC energy buffer are presented and compared with the original design. This paper also presents a comparison of unipolar and bipolar SSC energy buffers. It is shown that, although bipolar designs are superior in terms of effective energy density at low ripple ratios, unipolar designs can outperform bipolar designs at high ripple ratios. [ABSTRACT FROM PUBLISHER]

Electrolytic capacitors are often used for energy buffering applications, including buffering between single-phase ac and dc. While these capacitors have high energy density compared to film and ceramic capacitors, their life is limited. This paper presents a stacked switched capacitor (SSC) energy buffer architecture and some of its topological embodiments, which when used with longer life film capacitors overcome this limitation while achieving effective energy densities comparable to electrolytic capacitors. The architectural approach is introduced along with design and control techniques. A prototype SSC energy buffer using film capacitors, designed for a 320 V dc bus and able to support a 135 W load, has been built and tested with a power factor correction circuit. It is shown that the SSC energy buffer can successfully replace limited-life electrolytic capacitors with much longer life film capacitors, while maintaining volume and efficiency at a comparable level. [ABSTRACT FROM AUTHOR]