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Summary: A new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively. [ABSTRACT FROM AUTHOR]

Hybrid structure noise shaping (NS) SAR ADC combines both SAR ADC and sigma–delta ADC technologies with the advantages of high precision and low power consumption. In NS SAR ADC, mismatch error shaping (MES) method is used to solve the mismatch of low-level capacitors, and Data Weighted Averaging (DWA) method is used to solve the mismatch of high-level capacitors. The single-input comparator is improved into a dual-input comparator. The buffer and integrator circuits are realized by the static op-amp. The noise of op-amp is reduced by chopper technology and the accuracy of ADC is improved. A high-precision NS-SAR ADC with a sampling frequency of 1MSps and bandwidth of 25kHz was designed using the GSMC 90nm process. When the input signal is at full scale, the ENOB of the NS SAR ADC is higher than 14.73 bits, the SFDR is higher than 98dB, the average power consumption is 567.93μW and the quality factor is 169.2dB. [ABSTRACT FROM AUTHOR]

ABSTRACT This paper presents a novel angle track converter for sinusoidal encoders. These encoders provide electronic signals in which the position is encoded in sinusoidal form. This work aims to reduce the complexity and enhance the conversion speed of the sinusoidal‐to‐angle demodulation system. Considering the periodicity of sine and cosine signals (SCSs), the full range [0,2π)$$ \left[0,2\pi \right) $$ is evenly divided into eight segments to determine the coarse angle. According to the specific coarse angle segment, the SCSs are reshaped for proceeding demodulation. Then a fine angle is derived from reshaped signals based on division and arctangent algorithm. Division operation is achieved by a capacitor digital‐to‐analog converter, dynamic comparator, and successive approximation register. The arctangent value is obtained from the division result with the compensation by a small‐size look‐up table. The new converter fabricated in 0.18‐μ$$ \upmu $$m BCD technology occupies an active area of 0.16 mm2 and consumes 1.5 mW at the sample rate 10 MHz. The measured maximum error is 1.8°, in the full range. Without analog‐to‐digital converters and no nonlinear operation unit, the proposed angle track converter has a significant advantage in cost, speed, and efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a background calibration method assisted with noise-shaping, for a 10-b bridged SAR ADC. It proposes calibrating the mismatches from the MSB capacitors using the LSBs. First-order noise-shaping has been employed to facilitate the calibration as well as the analog-to-digital conversion. Since noise-shaping is able to shape both the comparator input and quantization noise, it is expected to improve the calibration effects as well as the SNR, for the SAR ADC. Measurement results show, upon the proposed calibration, the SAR's INL and SNR are improved by 3 LSB and 9 dB, respectively, compared to when the noise shaping is off. Fabricated using a 55 nm CMOS MOMCAP technology and tested with a −2.5 dB sinewave input, the bridged SAR ADC achieves an SNR of 62.2 dB and an INL better than 1 LSB, when consuming a power of 7 2 μ W , at a supply voltage of 1.2 V and sampling frequency of 50 kHz. The ADC's active area is 3 0 0 × 3 8 0 μ m 2 . [ABSTRACT FROM AUTHOR]

An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit, 4.5 MS/s synchronous SAR ADC implemented in SMIC's 130-nm CMOS technology. It features a novel method for internal common-mode (V cm) generation via introduces switched-capacitor technique, eliminating the need for external V cm generation circuitry and reducing parasitics. To enhance capacitor matching and mitigate mismatch, thermometer encoding is employed for the most significant 6-bit of the ADC. The comparator boasts a dynamic pre-amplifier with switching capacitance tail current for improved signal amplification. The ADC exhibits excellent linearity with DNL of +0.59/−0.57 LSB and INL of +1.02/−1.12 LSB. Occupying a core area of 0.144 mm2, it achieves SNDR of 69.63 dB, ENOB of 11.27-bit, SFDR of 78.17 dB, and THD of −76.33 dB. Operating at 3.3 V, it consumes 2.577 mW with FoM W of 231.9 fJ/conversion-step. These measurement results confirm the feasibility and effectiveness of the proposed V cm self-generation approach, offering fresh insights into V cm generation in ADC design, with potential implications for future ADC architectures. [ABSTRACT FROM AUTHOR]

This paper proposes a fully dynamic zoom ADC based on residue feedforward and correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) technique with 200 × bandwidth/power scalability, by only changing the clock frequency. A CLS-assisted FIA which achieves 65 dB DC gain is employed to reduce errors from finite FIA gain. An energy-efficient residue feedforward path extracted from the input of the SAR ADC's comparator minimizes the leakage of the SAR ADC's quantization noise into the band. A novel two-step summation approach is proposed to minimize capacitor areas compared to a traditional passive switched-capacitor adder. The post-simulated results show the prototype ADC with near-constant energy efficiency, which scales power from 5 μW to 822 μW, achieves high resolution (>100 dB) during the scalable bandwidth. At 20 kHz BW, it achieves 106.2 dB DR, 102.0 dB SNDR, leading to FoM DR of 180.0 dB and FoM SNDR of 175.8 dB. [ABSTRACT FROM AUTHOR]

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]

This article presents a one-stage buck converter with an accurate nanosecond ON-time ($T_{\mathrm{\scriptscriptstyle ON}}$) control for 48–1-V direct conversion for automotive applications. In order to overcome the low duty cycle from 48 to 1 V, the proposed high-voltage storage and low-voltage boost (HSLB) bootstrap circuit can reduce the level shifter delay to close to zero and the bootstrap delay to less than 2 ns. In addition, the early comparison $T_{\mathrm{\scriptscriptstyle ON}}$ generator can reduce the comparator delay ($T_{d\_{}{\mathrm{ comp}}}$) to close to zero at steady state to achieve precise nanosecond pulse $T_{\mathrm{\scriptscriptstyle ON}}$. On the other hand, $T_{d\_{}{\mathrm{ comp}}}$ can be quickly extended to increase $T_{\mathrm{\scriptscriptstyle ON}}$ by 540% to achieve fast transient with the recovery time of 3 $\mu \text{s}$ , in case load changes from 200 mA to 1 A. Based on the precise nanosecond $T_{\mathrm{\scriptscriptstyle ON}}$ , the OFF-time is extended by the load-dependent current limiting OFF-time modulation for improving light-load efficiency. Experimental results show that the peak efficiency reaches 96.5%, 95.1%, and 92.8% when $V_{\mathrm {IN}}$ is 12, 24, and 48 V, respectively, for $V_{\mathrm {OUT}} = 1$ V. [ABSTRACT FROM AUTHOR]

This article presents a fully passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that can be compatible with dynamic voltage and frequency scaling (DVFS) schemes while offering a 12-bit resolution for Internet-of-Things (IoT) sensor applications. To realize a voltage-scalable suppression of the in-band quantization noise, the proposed ADC utilizes a second-order cascade of integrators with feedforward (CIFF) NS loop with a 3-input dynamic comparator, which can obtain an additional resolution of more than 3 bits. A cyclic dynamic element matching (CDEM) for MSB is seamlessly combined with the NS operation and simply realized by shift registers (SRs). The MSB CDEM reduces dominant in-band harmonic distortions due to capacitor mismatch by not only averaging out but also randomizing the MSB mismatch errors with modulation dither from the CIFF NS loop. In addition, a last-bit majority voting (LMV) technique is applied when resolving the LSB to reduce the comparator noise by half with four additional cycles. With both the LMV and CDEM techniques enabled, the SNR and SNDR are enhanced to 73.3 and 72.3 dB, respectively. The ADC achieves an ENOB of $11.2-11.7$ bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V. The prototype ADC was fabricated using 28-nm CMOS technology, occupying an active area of 0.0575 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a 18-bit 1 MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15.7-bit. To achieve higher performance, a differential DAC utilizing both split and monotonic switching timing is designed. For both dynamic and static performance improvement, five techniques are proposed. First, a foreground digital self-calibration method based on normalized-full-scale-referencing is described to eliminate the capacitor mismatch errors. L-segment capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which further improve the ADC performance. Third, an adaptive-tracking-extra-bit-trail together with comparator noise extraction and correction for further accuracy enhancement is proposed. Forth, a harmonic calibration technique, which can efficiently attenuate 2-order and 3-order harmonic is introduced. Fifth, a comparator with ultra-low noise and offset is designed to meet the 18-bit 1-MS/s ADC. The ADC is fabricated in a 0.18-μm 5-V CMOS process. It measures a 96.1 dB SNDR and a 110.7 dB SFDR. The DNL and INL are within ±0.32 LSB and ±0.5 LSB, respectively. The overall power consumption of ADC core, drawn from the 5 V power supply, is 45 mW. [ABSTRACT FROM AUTHOR]

This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (SS) comparators, adding flexibility and power efficiency. The complete oversampling ADC is designed as a 3rd-order cascade of integrator with feed forward (CIFF) with a 4-bit quantizer, and it achieves a peak signal-to-noise and distortion ratio (SNDR) of 67 dB and DR of 70.0 dB with 47.5-MHz bandwidth when clocked at 950 MHz. This is the highest bandwidth reported to date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7 mW from a 1-V supply, figure of merit (FoM) Schreier and Walden are 167.0 dB and 27.0 fJ/c.s, respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth. [ABSTRACT FROM AUTHOR]

A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ($\Delta V_{\text {in}}$) is presented. Such adaptive operation significantly reduces the power of high-precision comparators in successive-approximation-register (SAR) ADCs. $\Delta V_{\text {in}}$ is integrated as a time difference via the VCO, where the integration continues as long as the time difference is below a certain threshold, defined by the phase detector deadzone. Thus, when $\Delta V_{\text {in}}$ is large, the comparator operates as a low-power delay line-based comparator, and with small $\Delta V_{\text {in}}$ , the VCO oscillates to integrate the input signal and suppresses the comparator noise. The required oscillations to complete the comparison are inversely proportional to $\Delta V_{\text {in}}$ , realizing fully adaptive noise and power scaling. This article provides a detailed analysis and specific design guidelines of the VCO comparator. Moreover, the PVT drift tolerance and detailed circuit implementations are deeply discussed as well. For proof-of-concept, a 13-bit SAR ADC with the proposed VCO-based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves peak SNDR 66 dB at 1 MS/s with a peak FoM of 29 fJ/conv.-step. [ABSTRACT FROM AUTHOR]

This work presents the design of a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and a positive feedback bulk structure. The output stage comprises a simple circuit to reduce the total voltage overhead necessary to define the logic levels. The powering scheme of the pre-amplifier, with a floating reservoir capacitor, contributes to reduce the impacts of global process variability. The positive feedback bulk structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also provides positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in a 28 nm CMOS technology and reaches an IRN below of the quantization noise of a 10 bits differential ADCs working with 600 mV power supply. The dynamic comparator achieves 237 μV input-referred noise, while consuming only 38.8 fJ per comparison and having a nominal delay of 5.77 ns. [ABSTRACT FROM AUTHOR]

This letter presents a novel high energy-efficient switching scheme with low common-mode level variation for successive approximation register (SAR) analog-to-digital converters. Benefit from the merge capacitor split and C-2C techniques, the proposed switching scheme achieves 98% saving in switching energy and 86.91% reduction in capacitor area over the conventional scheme without reset energy. Compared with state-of-the-art works, the area saving is the highest. Meanwhile, the common-mode level at the comparator input is Vcm except the second cycle and the last cycle during SAR ADC conversion phase, which reduces the dynamic offset of the comparator greatly. [ABSTRACT FROM AUTHOR]

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes $59.9~\mu \text{W}$ of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8. [ABSTRACT FROM AUTHOR]

This paper presents a 1 MHz PVT compensated dual phase relaxation Oscillator. The oscillator core employs a current controlled voltage bias replica circuit to limit the charging of capacitor. Furthermore, the current starved schmitt trigger circuit is employed in oscillator in place of conventional power consuming comparators. They also provide stable switching threshold voltage across temperature variations. The oscillator is designed in 90 nm STMicroelectronics BCD technology and validated to work for supply variations of 1.0–1.32 V and temperature range from − 40 to 175 °C to suitable for automotive, industrial as well as consumer applications. [ABSTRACT FROM AUTHOR]

Summary: This work presents a macro modeling approach for the time‐mode cyclic ADC. The proposed ADC macro model is realized using the time‐to‐voltage converter (TVC) and the voltage‐to‐time converter (VTC) that are the key building blocks of time‐mode ADCs. In addition, the effect of circuit nonidealities and error sources of the time‐mode ADC including parasitic capacitance, current source output resistance, switch on‐resistance, capacitor mismatch, and comparator offset are incorporated in the macro model. The simulation time of the proposed ADC macro model showed 87.1% reduction compared to the all transistor level ADC circuit. As a result, the proposed ADC macro model can facilitate the ADC design and leverage the ADC nonideality analysis. Furthermore, the proposed macro model can be used for ADC calibration scheme development. As a practical design example, the macro model for an 8‐bit time‐mode cyclic ADC has been realized, where the nonideality analysis, design optimization, and calibration scheme development based on the proposed macro model have been demonstrated. [ABSTRACT FROM AUTHOR]

This article reports a power-efficient $8\times $ time-interleaved (TI) 2.4-GS/s 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). To optimize the circuit design in terms of power efficiency and conversion rate, several enhancement techniques are presented. First, a pre-defined bypass window, introduced by the customized non-binary DAC, is used to modestly reduce the power consumption. Several conversion cycles are skipped as the input signal falls within the bypass window. Second, to enhance the operation speed, two alternate comparators are adopted in each ADC channel, and an opportunistic adaptive comparator offset calibration is proposed to eliminate the conversion rate degradation caused by the dedicated calibration cycle. The comparator offset is calibrated only when the bit bypass is triggered with the calibration step size adaptively set to acquire both fast convergence and small algorithm noise. In addition, the reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without the introduction of power-hungry-distributed reference buffers. A test chip is fabricated in a 28-nm fully depleted silicon on insulator (FDSOI) process with a core area of 0.11 mm2, including the reference charge reservoirs. Clocked at 2.4 GS/s, the proposed ADC measures a 49.02-dB signal-to-noise-and-distortion ratio (SNDR) at Nyquist while consuming only 9.8 mW from a 0.9-V supply, thus resulting in Walden and Schreier figures of merit (FOMs) of 17.7 fJ/conversion-step and 159.9 dB, respectively. [ABSTRACT FROM AUTHOR]

In this brief, a 300-mV, auto shutdown comparator based on a novel clock gating network is proposed. The proposed auto shutdown comparator is further employed to realize a compact, ultralow power continuous-time $\Delta \Sigma $ modulator (CTDSM) with a 300-mV supply voltage for multichannel sensing and biomedical applications. The design was fabricated in standard mixed-mode 180-nm CMOS process. Measurement results show that the CTDSM achieves a peak SNDR of 54.81 dB and DR of 57.4 dB while consuming a core power of $1.76~\mu \text{W}$ at 300-mV supply voltage without the clock-gated comparator. With the clock-gated auto shutdown comparator, the CTDSM consumes a core power of only 220 nW thereby providing an eight times power saving. Moreover, the fabricated CTDSM occupies an extremely small area of 0.0464 mm2 with an energy efficiency of 24.5 fJ/conv making it the most compact and energy-efficient CTDSM reported till date among the moderate resolution CTDSMs. Furthermore, by increasing the supply voltage to 400 mV, the CTDSM features a peak SNDR of 58.56 dB and DR of 64.1 dB while consuming a core power of 410 nW and 29.61 fJ/conv. [ABSTRACT FROM AUTHOR]

Purpose: Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach: A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET's and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings: The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value: The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as "spider-latch". [ABSTRACT FROM AUTHOR]

An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator. [ABSTRACT FROM AUTHOR]

Realizing the vision of a trillion IoT sensor nodes demands ultra low-power (ULP) compute, typically implemented using synchronous digital systems. These require low-power clock sources which must be fully integrated to meet low system-cost requirements. Hence, relaxation oscillators (RxOs) are popular. Their need for precision references and high-speed comparators can challenge power budgets; hence, prior works have explored low-speed closed-loop control for RxOs to alleviate this issue. This paper adopts an alternative approach to minimize the RxO power: the use of a ratioed switched-capacitor reference and sub-clock power-gating of the high-power comparator. The stability of the proposed design is further enhanced through the integration of digital-assist. This mixed-signal approach allowed a 1.2-MHz RxO to be implemented in 0.005 mm2 in TSMC 65 nm, with silicon measurements showing 0.7%/V line and 100 ppm/°C temperature stability. The energy-per-cycle figure of merit is 0.68 nW/kHz—a 4 $\times $ improvement over state-of-the-art for comparable stability. [ABSTRACT FROM AUTHOR]

A high energy-efficient and area-saving two-step switching method for the dual-capacitive arrays (DCAs) successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. By adopting two-step architecture, spilt-capacitor method, monotonic switching scheme, four-input comparator and C–2C capacitor array, the proposed procedure achieves 99.84% saving in average switching energy and 84.38% reduction in total capacitance compared to the conventional scheme when applied to a 10-bit SAR ADC, meanwhile achieving DNL and INL only 0.234LSB and 0.281LSB, respectively. Furthermore, this method eliminates reset energy, while achieves a compromise among energy, area, and linearity. [ABSTRACT FROM AUTHOR]

This paper presents a linearity-enhanced 10-bit 160-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a high-speed and low-noise comparator. A p-well floating technique for linearity improvement of sampling switch is proposed. The total parasitic capacitance of the sampling switch is depressed compared to conventional structures. Also, the variation of parasitic capacitance is reduced. Furthermore, a substrate voltage boosting technique is proposed to depress the noise of comparator at a high conversion rate. In addition, an improved parallel SAR logic is exhibited to increase the speed of SAR feedback loop and enhance the settling of digital-to-analog converter (DAC). Last, an adaptive sampling technique is utilized to increase the sampling time of SAR ADC. The proposed SAR ADC is fabricated in the 65-nm CMOS process, consuming 2 mW at a 1.2-V power supply. It achieves a signal-to-noise distortion ratio (SNDR) >55.6 dB and spurious-free dynamic range (SFDR) >69 dB at 160 MS/s. The ADC core occupies an active area of 0.023 mm2, and the corresponding figure-of-merit (FoM) is 25.4 fJ/conversion-step at Nyquist input. [ABSTRACT FROM AUTHOR]

In this brief, a relaxation oscillator with comparator delay compensation is presented. Two digital compensation loops are introduced to compensate for the comparator delay. This relaxation oscillator is fabricated in the 0.18- $\mu \text{m}$ CMOS process. The measured average oscillation frequency is 943.1 kHz. The whole oscillator consumes $5.2~\mu \text{W}$ under a 0.9-V supply. The measured average temperature coefficients (TCs) of the oscillation frequency with and without compensation are 93.88 and 618.17 ppm/°C, respectively. It achieves a TC improvement of $6.6\times $. The measured frequency variation is within ±0.7% from −10 °C to 100 °C by using the DCLs. The measured line sensitivity is 4.37%/V. The measured figure of merit (FOM2) is 173.3 dB. [ABSTRACT FROM AUTHOR]

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM. [ABSTRACT FROM AUTHOR]

A signal-dependent dithering calibration exploiting noise quantiser (NQ) technique to correct capacitor mismatch and inter-stage gain error in pipelined successive approximation register (SAR) ADCs is proposed. With signal-dependent dithering injection, capacitor mismatch and gain error are extracted and subsequently calibrated as one error in the background. Besides, a novel NQ is proposed for a dithering injection only when the residue is near the threshold of the comparator, thereby allowing the injection of dithering without consuming the dynamic range. The simulation results show that the calibration can significantly improve the performance of pipelined SAR ADCs without extra hardware overhead and timing budget. [ABSTRACT FROM AUTHOR]

In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated. [ABSTRACT FROM AUTHOR]

Abstract This paper configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100% energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N -bit SAR ADC shows a 50% capacitor area reduction in comparison with the conventional SAR ADC. [ABSTRACT FROM AUTHOR]

Abstract A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC. [ABSTRACT FROM AUTHOR]

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$. The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz. [ABSTRACT FROM AUTHOR]

A latch-type comparator with a dynamic bias pre-amplifier is implemented in a 65-nm CMOS process. The dynamic bias with a tail capacitor is simple to implement and ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator is analyzed and compared to its prior art in terms of energy consumption and input referred noise voltage. First-order equations are presented that show how to optimize the pre-amplifier for low noise and high gain. Both the dynamic bias comparator and the prior art are implemented on the same die and measurements show that the dynamic bias can reduce the average energy consumption by about a factor 2.5 for the same input-equivalent noise at an input common-mode level of half the supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, two essential components of the Flash ADC are designed and integrated within a new Flash ADC architecture. The power consumption is reduced by realizing a switched-capacitor positive feedback (SCPF) comparators structure as a replacement for conventional comparators structure. The SCPF comparator is tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision. Furthermore, the encoding stage is implemented using N parallel independent components of one single AND gate each, where N is the number of quantized regions. This structure provides fast encoding with minimal encoding activities. The design architecture exploits two stages, which are separated by latches. The first stage allocates the analog input to a quantized region, while the second stage converts the level of the quantized region into its corresponding binary code. This separation is considered the key success for incorporating the SCPF comparators structure into our Flash ADC architecture. HSPICE simulations of the proposed design use 35 nm Synopsys FinFet technology and 1-V power supply. The simulation results show that our 5-bit Flash ADC can function at a sampling frequency of up to 1 GHz, with an input signal of 500 MHz at Nyquist rate, where the amplitude input signal is ranging from 0.2 to 0.8 V with an overall maximum power consumption of 3 mW. [ABSTRACT FROM AUTHOR]

A bypass-switching successive approximation (BSSA) register analog-to-digital converter (ADC) employing a newly proposed dynamic proximity comparator is presented in this paper. By exploiting the current characteristics of a current correlator, the proposed comparator generates the bypass signal directly along with the polarity comparison result. The bypass window size can be adjusted to optimize the power reduction for different sensing applications with low-voltage sensitivity. A BSSA logic circuit is adopted with reduced number of logic gates as well as switching power. A prototyped chip including a proposed ADC has been designed and fabricated in a 0.18- \mu \textm CMOS process occupying an area of 0.041 mm2. With a supply voltage of 0.6 V and at a sampling rate of 50 kS/s, the measured signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 56.9 and 68.7 dB, respectively, achieving an effective number of bits (ENoB) of 9.16. The ADC consumes power of 114 nW while digitizing sinusoidal inputs. With a bypass window size of ±32 LSBs, the designed ADC consumes only 76 nW when quantizing full-scale electrocardiography signals that are generated from a certified commercial simulator, exhibiting a figure-of-merit (FoM) of 2.66 fJ/conversion-step. Besides ECG signals, the ADC is also demonstrated by digitizing electromyography and electrooculography signals from human bodies. [ABSTRACT FROM AUTHOR]

This paper presents a capacitor sample-hold oscillator architecture which realizes temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. Due to its dual-way charging and discharging structure, the peak charge voltage for each phase will eventually stabilized around half the supply voltage. The frequency of the oscillator depends on the RC time constants of capacitors charging (discharging) across passively-temperature-stabilized resistive elements and the comparator delay time. By analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents to achieve temperature stabilization of the delay time, this architecture improves the overall temperature stability. This architecture has been designed and verified in 0.18-μm CMOS technology. The simulation results demonstrate this design consumes 7.99 μW from a 1.8 V supply voltage at 58.9 kHz and achieves a temperature stability of best 22.19 ppm/℃(TT Corner) from −40◦C to 90◦C, and frequency variations of ± 0.3 % for supply changes from 1.25 to 1.8 V. [ABSTRACT FROM AUTHOR]

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm. The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Charge scaling data converters include a binary-weighted capacitor array in their structure. New methods for the placement and sizing of capacitor arrays with increased ratio accuracy and improved converter linearity are presented in this paper. A new model of statistical variation is used, which takes into account both spatial correlation between devices and device area. This is combined with a novel analytical model for the linearity metrics of a charge scaling digital-to-analog converter. Minimizing the variance of the linearity metrics directs a new chessboard placement method for the capacitor array. Chessboard placement is shown to be superior to the state of the art in consideration of both random and systematic mismatch. The new analytical model is then used to develop a flow for capacitor array sizing. [ABSTRACT FROM PUBLISHER]

The propagation of Analog Single Event Transients (ASETs) to multiple outputs of Bipolar Junction Transistor (BJTs) Integrated Circuits (ICs) is reported for the first time. The results demonstrate that ASETs can appear at several outputs of a BJT amplifier or comparator as a result of a single ion or single laser pulse strike at a single physical location on the chip of a large-scale integrated BJT analog circuit. This is independent of interconnect cross-talk or charge-sharing effects. Laser experiments, together with SPICE simulations and analysis of the ASET’s propagation in the s-domain are used to explain how multiple-output transients (MOTs) are generated and propagate in the device. This study demonstrates that both the charge collection associated with an ASET and the ASET’s shape, commonly used to characterize the propagation of SETs in devices and systems, are unable to explain quantitatively how MOTs propagate through an integrated analog circuit. The analysis methodology adopted here involves combining the Fourier transform of the propagating signal and the current-source transfer function in the s-domain. This approach reveals the mechanisms involved in the transient signal propagation from its point of generation to one or more outputs without the signal following a continuous interconnect path. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive investigation of several important error sources for the successive-approximation register (SAR) analog-to-digital converters (ADCs). The error sources that we discuss in this paper include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential nonlinearities (INL/DNL) of SAR ADCs that are resulted from these error sources are analyzed and addressed. A diagnostic procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also offered and recommended in this paper. [ABSTRACT FROM AUTHOR]

This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in a low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes the DAC settling time requirement and makes it possible to insert a minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances the noise performance of the comparator and a self time-reference generation function is embedded in the pre-amplifier for a speed-enhanced asynchronous decision. A proposed dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-but-low-quality clock for low-frequency operation. With the dual-mode clock generator enabled, a prototype 65 nm CMOS 0.6 V 12 b 10 MS/s ADC achieves an ENOB of 10.4 at a Nyquist-rate input, and the peaks of DNL and INL are measured to be 0.24 LSB and 0.45 LSB, respectively. The FoM is 6.2 fJ/conversion-step with a power consumption of 83~\mu \text W . The ADC operates under the lowest supply voltage of 0.6 V among comparable designs with ENOBs over 10 and conversion rates over 1 MS/s. [ABSTRACT FROM AUTHOR]

When operating at scaled supply voltages, the primary source of performance degradation in a successive approximation register (SAR) analog-to-digital converter (ADC) is the comparator thermal noise. Low-noise comparator can be used but at the expense of increased power dissipation. This paper presents an approach to reduce the comparator power in SAR ADCs. A mathematical model of a SAR ADC derived in this paper suggests that using the same comparator noise variance for each bit cycle is suboptimal and results in more power consumption than necessary. A noise programmable comparator based on majority vote technique is proposed to adjust the comparator noise performance at each bit step. As a proof of concept, a 10-bit SAR ADC that operates at 0.5-V supply voltage and supports a flexible differential input dynamic range from 0.4 to 1 V has been fabricated in 65-nm CMOS process. The prototype achieves an effective number of bits ranging from 7.1 to 9.1 bits and a figure of merit from 3.3 to 6.8 fJ/conversion step while operating at 250 kS/s. [ABSTRACT FROM PUBLISHER]

The ring amplifier is an energy efficient and high output swing alternative to an OTA for switched-capacitor circuits. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. This paper presents a self-biased ring amplifier scheme that makes the ring amplifier more practical and power efficient while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. We introduce an improved auto-zero scheme that eliminates the gain error caused by the parasitic capacitance across the auto-zero switch. Furthermore, a comparator-less pipeline ADC structure takes advantage of the characteristics of the ring-amplifier to replace the sub-ADC in each pipeline stage. The prototype ADC has measured SNDR, SNR and SFDR of 56.6 dB (9.11 b), 57.5 dB and 64.7 dB, respectively, for a Nyquist frequency input sampled at 100 MS/s, and consumes 2.46 mW. [ABSTRACT FROM PUBLISHER]

A dual-slope capacitance-to-digital converter for pressure-sensing is presented and demonstrated in a complete microsystem. The design uses base capacitance subtraction with a configurable capacitor bank to narrow down input capacitance range and reduce conversion time. An energy-efficient iterative charge subtraction method is proposed, employing a current mirror that leverages the 3.6 V battery supply available in the system. We also propose dual-precision comparators to reduce comparator power while maintaining high accuracy during slope conversion, further improving energy efficiency. The converter occupies 0.105 mm^2 in 180 nm CMOS and achieves 44.2 dB SNR at 6.4 ms conversion time and 110 nW of power, corresponding to 5.3 pJ/conv-step FoM. The converter is integrated with a pressure transducer, battery, processor, power management unit, and radio to form a complete 1.4 mm\times 2.8 mm \times 1.6 mm pressure sensor system aimed at implantable devices. The multi-layer system is implemented in 180 nm CMOS. The system was tested for resolution in a pressure chamber with an external 3.6 V supply and serial communication bus, and the measured resolution of 0.77 mmHg was recorded. We also demonstrated the wireless readout of the pressure data on the stack system operating completely wirelessly using an integrated battery. [ABSTRACT FROM AUTHOR]

A new current-comparator-based dual-channel calibration system for AC currents and AC voltages in the millivolt range has been developed. The range of generated currents is 1 mA–5 A, and the range of generated voltages is 1–500 mV. The calibration system in-phase and quadrature expanded measurement uncertainties ( $k=2$ ) are within 25\cdot 10^{\mathrm {\mathbf {-6}}} . Although the system has been developed primarily for operation at power frequencies, it is also capable of operating at frequencies up to 1000 Hz with slightly increased uncertainties. The traceability to SI units is established through the calibration of AC voltage by means of AC/DC transfer and DC voltage reference, standard resistor, capacitor, and current comparator ratios. [ABSTRACT FROM PUBLISHER]