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In this paper, a simple controller configuration for the decentralized parallel operation of single-phase inverters in stand-alone ac supply systems is proposed. The configuration is designed considering the unavailability of the filter capacitor voltage and grid current information to the controller. Due to the unavailability of voltage information, internally estimated voltage references and the measured value of the converter-side inductor current are used for the calculation of the active and reactive power. Frequency and voltage droop characteristics are used, and hence, communication is not required. The operation of the inverter at the reference voltage magnitude and frequency is achieved by the direct control of the modulating wave. Therefore, inability to implement closed loops caused by the absence of certain voltage and current information is mitigated. The proposed controller has the provision for protection of switching devices during overcurrent situation. The accuracy and feasibility of the proposed controller are validated using the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Cascaded multicell converter (CMC) is proved to be an effective solution for medium voltage drives. Three-phase diode bridge rectifiers are normally used in this converter, which do not have regeneration capability. Pulsewidth-modulated (PWM) rectifier-based power cells enable the drives with regeneration capability. However, due to their two-level voltage operation at the input side, an inductor is required for each cell to filter out the switching frequency components from the input current. In this paper, a new configuration with single-phase PWM rectifier-based power cell is proposed to achieve multilevel voltage operation at both the input and output sides of the converter. Therefore, the devices at the rectifier side are also operated at reduced switching frequency without using any filter inductor for each cell. In the proposed converter, simple modular transformers are used instead of a single large and complex transformer that is used in the conventional CMC. Further, input phase currents of the converter are controlled in the synchronously rotating d–q frame, which requires only two current sensors at the input side instead of individual current sensors for each cell. Experimental validation of the proposed converter configuration is carried out on a 4.5-kVA prototype, and the results are presented. [ABSTRACT FROM PUBLISHER]

High efficiency and operating life of grid feeding solar photovoltaic (PV) inverters are demanded. Due to reduced dc-link capacitor requirement, current source inverter (CSI) offers higher reliability than the voltage source based solar inverter. However, conventional three-phase pulse width modulated (PWM) current source based solar inverter injects high earth leakage current into the grid. In order to suppress this current, an isolation transformer can be used. Use of this transformer increases the cost and size, and decreases overall efficiency. In order to address the aforementioned limitations, a modified CSI is proposed in this paper. The proposed inverter suppresses the earth leakage current without using an isolation transformer, thereby increasing the efficiency and reducing cost as compared to conventional current source based solar inverters. A mathematical model of the system is derived based on which controller for the operation of the inverter is designed. The effectiveness of the scheme is verified through detailed simulation study. To confirm the viability of the scheme, experimental studies are carried out on a scaled-down laboratory prototype. [ABSTRACT FROM PUBLISHER]

In this paper, a simple static var compensating scheme using a cascaded two-level inverter-based multilevel inverter is proposed. The topology consists of two standard two-level inverters connected in cascade through open-end windings of a three-phase transformer. The dc-link voltages of the inverters are regulated at different levels to obtain four-level operation. The simulation study is carried out in MATLAB/SIMULINK to predict the performance of the proposed scheme under balanced and unbalanced supply-voltage conditions. A laboratory prototype is developed to validate the simulation results. The control scheme is implemented using the TMS320F28335 digital signal processor. Further, stability behavior of the topology is investigated. The dynamic model is developed and transfer functions are derived. The system behavior is analyzed for various operating conditions. [ABSTRACT FROM AUTHOR]

A four-level static compensator integrating two 2-level converters, supplying/absorbing reactive power to/from the grid, is reported in our earlier paper. Reduced component count, simpler layout for switches, and smaller dc-link capacitor values are the attractive features of the proposed topology over the diode clamped and cascaded multilevel converters. This paper suggests further improvements in this topology. Suitable selection of the dc-link voltage values reduces distortion in the current fed to the grid. In addition, circuit topology is modified to avoid the split-capacitor dc links. This reduces the number of independent dc capacitor voltages to be controlled and eliminates the flow of third-harmonic current through the transformer. In order to improve the performance, a phase-shifted carrier-based pulsewidth modulation technique is used. A mathematical model of the system is derived, based on which a controller for the scheme is designed. The effectiveness of the scheme is verified through detailed simulation study. To confirm the viability of the scheme, experimental studies are carried out on a scaled-down laboratory prototype developed for the purpose. [ABSTRACT FROM PUBLISHER]

A three-phase three-level dc-to-dc phase-shifted pulsewidth-modulation (PSPWM) converter which is reported in the literature for high-power and high-input-voltage applications is based on a three-phase three-wire configuration. However, the controllable duty cycle range of the aforementioned converter is 0– 2\pi/3. Therefore, to obtain the rated voltage, the converter needs to be overrated by 33%. In order to overcome this problem, a modified topology of the three-level dc-to-dc PSPWM converter based on a three-phase four-wire configuration is proposed. The soft switching of devices is achieved by using a tapped filter inductor. The output voltage is controlled by incorporating PSPWM. The clocked gate signals of each leg are phase shifted by 2\pi/3 from each other. Major features of the converter include the following: 1) The outer two switches of each leg are operating as zero-voltage switch; 2) the inner two switches of each leg are operating as zero-current switch; and 3) this is achieved without involving any extra passive or active components. Realization of the secondary output filter by having a tapped inductor leads to considerable reduction in circulating current flow during a freewheeling period and results in appreciable mitigation in conduction losses. In order to obtain the behavioral and performance characteristics of the converter topology, analytical and simulation studies are carried out, and the viability of the scheme is ascertained through detailed experimental studies. [ABSTRACT FROM AUTHOR]

A novel soft-switched quasi-resonant dc-link (QRDCL) inverter topology is derived using the concept of an auxiliary switch-assisted soft-switcher (AASS) employing the flying capacitor. This concept is known for its high efficiency at high power levels, and is used for soft-switching the boost switch in zero-voltage transition (ZVT) power factor correction (PFC) boost rectifiers. Also, an active clamp circuit configuration to clamp the dc-link and recover the energy stored in the clamp capacitor is introduced and is applied to the proposed inverter topology. The resultant inverter configuration gives high efficiency and is suitable for high power motor drive applications. The maximum dc-link voltage is clamped at around (1.05–1.1) times the input dc-source voltage. The proposed inverter is suitable for pulse width modulation (PWM) operation. A detailed analysis along with the design procedure of the proposed inverter is presented. Simulation and laboratory experiments are carried out to validate the analysis. [ABSTRACT FROM AUTHOR]