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This paper proposes a novel 49-level stacked inverter topology for drives. The 49 levels are achieved by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading a flying capacitor (FC) inverter with three capacitor-fed H-bridges. The device count can be reduced by making the FC and the three cascaded H-bridges common to the dc link in each phase using selector switches in between them. The selector switches need to operate at fundamental frequency only. Also, the devices need to block very low voltages. Hence, MOSFETs can be used. This topology requires three dc sources, each of V\text{dc} /6 only, which can be replaced with stacked batteries for electric vehicle applications. The reduction in the dc voltage requirement is achieved by using a normal symmetric six-phase induction motor with parallel connection of the opposite phase windings. All the floating capacitors in the topology can be balanced irrespective of any modulation index or load power factor. Due to the high number of voltage levels, nearest level control can be used instead of pulse width modulation, which reduces the switching losses. The $dv/dt$ during the inverter operation is also less. Detailed experimental results at different speeds of operation and during transients ensure that the novel topology can be a viable option for high-power adjustable speed drives. [ABSTRACT FROM PUBLISHER]

This paper investigates the influence of a constant carrier phase shift on the DC-link capacitor harmonic current of cascaded converters used in fuel-cell and mild-hybrid electric vehicles. In these applications, a DC-DC converter can be adopted between the battery and the motor drive inverter in a cascaded structure, where the two converters share the same DC-link. Since the DC-link capacitor of such a system represents a critical component, the optimization of the converter operation to limit the current stress and extend the lifetime of the capacitor is an primary objective. This paper proposes the use of a carrier phase shift between the modulations of the two converters in order to minimize the harmonic current of the DC-link capacitor. By harmonic analysis, an optimal carrier phase shift can be derived depending on the converter configuration. Analytical results are presented and validated by hardware-in-the-loop experiments. The findings show that the pulse width modulation carrier phase shift between the interleaved boost converter and the voltage source motor drive inverter has a significant influence on the DC-link capacitor current and thus on its lifetime. A case study with two-cell and three-cell interleaved boost converters shows a possible DC-link capacitor lifetime extension of up to 390%. [ABSTRACT FROM AUTHOR]

In this work, a multilevel 42-sided polygonal space vector structure for suppression of lower order harmonics for open-end induction motor (OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an OEIM from either side. The main inverter fed with a single dc-link providing active power for motoring operation is switched at low switching frequency. The secondary inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the dc-link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures, are combined with multilevel inverter topology. This offers various advantages like multilevel operation with low inverter switching for the main power delivery inverter and harmonic suppression throughout the modulation range. The low switching frequency primary inverter generates harmonics of the order $6*k \pm 1$ , where $k = 1, 2, 3,{\ldots }$. The harmonics are suppressed by the capacitor-fed secondary inverter, which supplies only reactive power for suppression of lower order harmonics in motor phase voltage. Use of a single dc-link facilitates four-quadrant operation of the inverter. The proposed scheme is validated for steady-state and dynamic performance by experimental results. [ABSTRACT FROM AUTHOR]

In this article, a nonlinear high-gain observer (NHGO)-based second-order sliding mode (SOSM) control strategy is proposed for the three-phase three-level neutral-point-clamped (NPC) converter. This controller applies the advanced SOSM algorithm both in the voltage regulation loop and in the power tracking loop, which provides a fast dynamic for the dc-link voltage, and also assures a good steady-state behavior for the NPC converter. Additionally, an NHGO technique is implemented in the voltage regulator combining with the SOSM algorithm. The conventional observer-based controllers suffer from the destructive effects of measurement noise, and it can only be addressed by diminishing the observer gain, which sacrifices the observer property. The NHGO technique adopts a time varying gain, that is, high gain in transient while low gain in steady state, which minimizes the adverse influence of measurement noise. The tuning method of the proposed NHGO-based SOSM controller is given to simplify the implementation process. Finally, the simulation and experimental results of the proposed control scheme for the NPC converter are given and compared with the conventional PI controller as well as the well-known linear extended state observer-based control method, which validates the feasibility and superiority of the proposed controller. [ABSTRACT FROM AUTHOR]

This article proposes a sliding-mode-observer (SMO)-based control strategy to regulate the dc-link voltage for a three-phase two-level active front end (AFE). The SMO is designed for the voltage control loop to estimate the external load which is abruptly connected to the AFE dc-link and consequently causes the dc-link voltage fluctuation. The estimated load value is used to compensate the voltage loop controller, therefore, the voltage loop gains more robustness against the load perturbation and its disturbing effect is greatly reduced. The effectiveness and advantage of the proposed control strategy has been verified through theoretical analysis, simulations, and the real-application experiments conducted on a 5 KVA laboratory AFE. The results show that the proposed control strategy provides obvious improvement of the dc-link voltage control performance comparing with the conventional PI controller and demonstrates stronger robustness against the operating point variations caused by the changes in external load and dc-link capacitance. [ABSTRACT FROM AUTHOR]

Modular multilevel converters have become the prominent topology for medium- and high-voltage applications. The performance of these converters highly depends on the accuracy of the used modulation approach, for which the capacitor voltage of submodules (SM) are usually assumed to be equal. This article exhibits that ignoring the capacitor voltage differences among SMs adversely affects the system performance. This becomes more obvious the larger the capacitor voltage differences are. Hence, this article proposes a more accurate feedforward modulation approach that takes into account either the instantaneous capacitor voltage value and the real output voltage in the modulation stage. As a result, in applications where larger SM voltage differences are expected, the current distortion and control performance are improved. Particularly, switching–saving approaches benefit from this method as it enables their operation with reduced switching losses without the downsides of increased distortion due to capacitor voltage differences. The proposed approach is analyzed and compared with the nearest-level modulation and with the level-shift PWM. Simulations and experimental validation are presented to confirm the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

This article proposes an inverter topology for the first time for suppression of all lower order harmonics (5th, 7th, 11th, 13th, etc.) up to 39th harmonic. The lower order harmonic suppression is achieved by switching the 42-sided polygonal vectors, which eliminates harmonics in phase voltage without using a passive LC filtering technique. The power circuit topology uses a single dc-link supply for the primary inverter. The secondary inverter is fed with a capacitive supply. A novel topology is proposed for the dense six-level secondary inverter. The lower order harmonics in phase voltage are suppressed using the secondary inverter, which acts like a switched-capacitive filter. This article also proposes a novel capacitor voltage-balancing scheme for the first time, which achieves voltage balancing for secondary inverter capacitors. The voltages of secondary inverter capacitors are balanced using the power balance relationship between the primary inverter and the motor load. An experimental study of the topology and the capacitor-balancing scheme is presented for the validation of proposed scheme. [ABSTRACT FROM AUTHOR]

This article proposes a new control method for modular multilevel converter (MMC), which is based on a modification of the conventional nearest level control (NLC) scheme implemented by a model predictive control (MPC) technique. Applying the proposed method, the simplicity of the NLC is maintained while the current control ability in terms of both phase current and circulating current is enhanced by the MPC technique. A proper rounding function is used for each arm of the MMC instead of the conventional nearest integer function. The rounding function is determined by evaluating a cost function within the frame of MPC. To validate the proposed technique, a three-phase MMC prototype is employed. The conventional NLC-based control approach of MMC is also evaluated for comparative purposes. Results show that the proposed method exhibits excellent current-regulating ability. Compared with the conventional control scheme, the overall performance is improved without significantly increasing the computational burden or adding relevant complexity to the control system design. [ABSTRACT FROM AUTHOR]

This paper presents voltage regulation and current tracking control strategies for three phase two-level grid-connected power converters. By using power-invariant Park’s transformation, an averaged mathematical model of power converters is obtained in dq synchronous reference frame. Then a novel control strategy using adaptive control and ${H}_{\infty }$ technique is proposed to regulate the dc-link output voltage as well as track a desired current reference for three-phase power rectifiers. More specifically, an efficient adaptive controller is established in the external loop for regulating dc-link output voltage in the presence of external disturbances. A set of ${H}_{\infty }$ controllers are designed in the internal loop to force the input currents track their desired values. Finally, simulation results obtained from the proposed control method are presented, analyzed, and compared with that of sliding mode control, and the superiority of the proposed control laws is verified. [ABSTRACT FROM AUTHOR]

This article presents a dc solid state transformer based on three-level power module (PM) (TL-DCSST) for interconnection of medium-voltage dc (MVdc) and low-voltage dc distribution system. The proposed TL-DCSST adopts the low-voltage insulated-gate bipolar transistor (IGBTs) with excellent switching characteristics to build medium voltage PM and reduces the number of medium frequency transformer (MFT). This topology features inherent antibias mechanism for MFTs on the primary side, which saves the resonant capacitor at primary side. Meanwhile, the active front end is integrated to realize voltage and power regulation, low voltage ride-through and DC fault handling for MVdc side. In this article, the topology, operation principle, interleaving modulation, circuit parameter design, and control schemes are presented and analyzed comprehensively. At last, a prototype rated at 7 kW has been built and tested, and the experimental results verify effectiveness of the proposed TL-DCSST. [ABSTRACT FROM AUTHOR]

In this article, a model predictive control (MPC) strategy based on the optimal switching sequence (OSS) concept for a single-phase grid-connected H-bridge neutral-point-clamped (H-NPC) power converter is presented. The proposed OSS-MPC algorithm considers both the grid current tracking error and the dc-link capacitor voltage balance. Special emphasis is placed on the power converter control region in order to design suitable switching sequence candidates for this multiobjective control problem. Additionally, based on an analysis of the weighting factor effect over closed-loop performance, it is possible to demonstrate that this controller parameter is relatively easy to adjust. In fact, the weighting factor only affects the peak current during transients, with no effect over the steady-state performance. As a result, the proposed OSS-MPC provides a fast closed-loop dynamic to the H-NPC converter, which operates with a fixed switching frequency at all times. This predictive control strategy is experimentally validated in a 3.5-kVA laboratory setup. [ABSTRACT FROM AUTHOR]

This paper proposes a novel control strategy for three-level neutral-point-clamped (NPC) power converter. The proposed control scheme consists of three control loops, i.e., instantaneous power tracking control loop, voltage regulation loop, and voltage balancing loop. First, in the power tracking control loop, a set of adaptive sliding mode controllers are established to drive the active and reactive power tracking to their desired values via radial basis function neural network technology. In the voltage regulation loop, an efficient but simple adaptive controller is designed to regulate dc-link output voltage where the load is considered as an external disturbance. Moreover, a composite controller is developed in the voltage balancing loop to ensure imbalance voltages between two dc-link capacitors close to zero, in which a reduced-order observer is used to estimate sinusoidal disturbance improving the converter performance. The effectiveness and superiority of the proposed control strategy for the NPC power converter are compared with other control schemes through experimental results. [ABSTRACT FROM AUTHOR]

A new approach to the control of three-phase two-level grid-connected power converters is proposed in this paper. The proposed control is an extended state observer (ESO)-based second order sliding mode (SOSM), which comprises two control loops: the outer loop is a voltage regulation loop, as well as inner loop is an instantaneous power tracking loop. The outer loop is accomplished by an ${H}_{\infty }$ controller plus an ESO, which is designed to regulate dc-link capacitor voltage of the converter and asymptotically reject external disturbances and parameter perturbations. The SOSM strategy is employed in the inner loop to drive the active and reactive power convergence to their desired values. Control objectives of nearly unity power factor and dc-link capacitor voltage regulation are simultaneously satisfied. Availability of the ESO-based SOSM is compared with the classic proportional-integral control in simulations, and the comparison implies that the proposed strategy not merely achieves an almost perfect tracking performance, but also provides a complete robustness against resistance load variation. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

This paper proposes an extended state observer (ESO) based second-order sliding-mode (SOSM) control for three-phase two-level grid-connected power converters. The proposed control technique forces the input currents to track the desired values, which can indirectly regulate the output voltage while achieving a user-defined power factor. The presented approach has two control loops. A current control loop based on an SOSM and a dc-link voltage regulation loop which consists of an ESO plus SOSM. In this work, the load connected to the dc-link capacitor is considered as an external disturbance. An ESO is used to asymptotically reject this external disturbance. Therefore, its design is considered in the control law derivation to achieve a high performance. Theoretical analysis is given to show the closed-loop behavior of the proposed controller and experimental results are presented to validate the control algorithm under a real power converter prototype. [ABSTRACT FROM PUBLISHER]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (Vdc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme. [ABSTRACT FROM PUBLISHER]

A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation. [ABSTRACT FROM AUTHOR]

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc. [ABSTRACT FROM AUTHOR]

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor. [ABSTRACT FROM AUTHOR]