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This brief presents a fully integrated low-power, low noise bandgap reference (BGR) with load driving capability. With the BGR core resistors functioning as the feedback network of the current sourcing power transistor, the proposed BGR saves chip area, reduces noise while supporting current load driving. The circuit is implemented in two different processes for performance comparison, namely the $0.18\mathbf {\mathrm {\mu }}\text{m}$ RF CMOS and the BCD mixed-signal CMOS processes. Measurement results from chip samples of the two processes show similar performances, with an average temperature coefficient (TC) of 27.1ppm/°C over $\mathbf {-} 40\mathbf {\mathrm {\sim }} 125\mathbf {^{\circ} }\text{C}$ at a 1.8-V supply. The corresponding measured coefficient of variation ($\mathbf {\mathrm {\sigma }}/\mathbf {\mathrm {\mu }}$) is around 0.3%, and the load driving capability can be up to $800\mathbf {\mathrm {\mu }}\text{A}$. By reusing the feedback resistors, the chip prototype achieved a low noise density of $1.92~\mathbf {\mathrm {\mu }}\text{V}/\surd $ Hz, 285nV/ $\surd $ Hz and 4nV/ $\surd $ Hz at 10 Hz, 10 kHz and 100 kHz, respectively, while consuming a quiescent current of 396nA. The measured power supply rejection (PSR) is −39dB at 5Hz and −45dB at 1MHz. The influence of load current on PSR has also been analyzed and verified. [ABSTRACT FROM AUTHOR]

This article presents an arithmetic progression (AP) switched-capacitor (SC) dc–dc converter topology for systematic step-down reconfigurable rational voltage conversion ratio (VCR) generation while exhibiting soft VCR transitions and quasi-symmetric two-phase charge delivery. The proposed AP topology features fixed steady-state voltage in all the flying capacitors ($C_{\mathrm {FLY}}$) irrespective of VCR change, essentially eliminating the internal $C_{\mathrm {FLY}}$ hard-charging loss due to voltage rebalancing, effectively improving the overall dynamic efficiency. It also achieves optimal steady-state slow-/fast-switching loss. Furthermore, due to the inherent quasi-symmetric output charge ($Q_{\mathrm {OUT}}$) delivery property in the two-phase switching operations, the proposed topology alleviates the VCR-dependent imbalanced per-phase $Q_{\mathrm {OUT}}$ delivery to relax the $C_{\mathrm {OUT}}$ requirement in a single-branch converter implementation. We propose a cross-coupled bootstrapping driver (XCBD) operated at half of the converter switching frequency ($f_{\mathrm {SW}}$) to adaptively control the flying power switches without relying on dual-branch interleaved architecture. Fabricated in 65-nm CMOS, the implemented AP chip prototype achieves a step-down VCR of 5:4/3/2/1 and converts a 1.5-V input to a 0.18–1.19-V output. With a measured steady-state peak power conversion efficiency (PCE) of 93.7%, this work can deliver a maximum output current of 400 mA while attaining an average conversion efficiency of up to 89% under a periodic VCR transition at 100 kHz as benefitted from the intrinsic soft VCR transition and low conduction loss properties. [ABSTRACT FROM AUTHOR]

This tutorial brief reviews highly-integrated switched-capacitor (SC) DC-DC converter topologies for miniaturized energy harvesting (EH) IoT systems. Aiming to provide a concise overview of SC converter-based EH interfaces, we first discuss the system level design considerations for energy balancing between source, storage, and load under different environmental conditions. The key factors dominating the energy extraction and power conversion efficiencies, including the source adaptation strategies and SC power stage intrinsic losses, are outlined to establish a fundamental understanding on the EH system performance. After studying different state-of-the-art SC topologies in terms of their rational boost voltage conversion ratio (VCR) generation flexibility, loss characteristics, and implementation tradeoffs, we further introduce two advanced SC converter-based EH system examples, highlighting the SC converter operation in enhancing the EH system functionality and performance. The pros and cons of different SC converter topologies for EH systems will also be discussed. [ABSTRACT FROM AUTHOR]

This brief describes a fully integrated 10-V pulse driver. It comprises a four-stage switched-capacitor voltage multiplier (SCVM) and a dedicated high-voltage output driver (HVOD) with multiband pulse-frequency modulation (MPFM) to generate efficiently 10 V regulated output pulses. Specifically, an analog/digital hybrid-controlled current-starved ring oscillator (HCRO) modulates the switching frequencies at distinct bands to regulate the high-voltage (HV) supply for the HVOD, while enabling fast output transitions with an improved driving efficiency. Prototyped in 65-nm bulk CMOS, the driver demonstrates 10-V pulse generations over a 0.1-to-1-MHz range for a 15 pF//50 kΩ load. With the proposed MPFM, this work measures an overall driving efficiency of up to 19.9%, corresponding to a ~1.6 × improvement over prior arts. The measured output rise time of 119 ns is also ~25% faster when compared with using the conventional pulse-frequency modulation (PFM) scheme. [ABSTRACT FROM AUTHOR]

This article proposes a split-phase flipping-capacitor rectifier (SPFCR) to resolve the hard tradeoff between the number of capacitors and the energy-extraction efficiency for capacitive piezoelectric energy-harvesting (PEH) interfaces. By splitting the capacitor usage into multiple phases, this article can achieve the most number of flipping phases using the same number of capacitors when compared with the state of the art. We also relaxed the implementation complexity by removing insignificant SFPCR flipping phases without sacrificing the energy-harvesting efficiency. To improve further the input power adaptation, the flipping capacitors are reconfigured as a multiple-voltage-conversion-ratio (MVCR) switched-capacitor dc–dc converter during the non-flipping period without using extra passives. Maximum-power-point tracking (MPPT) is also accomplished using the full-bridge rectifier (FBR) fractional open-circuit voltage ($V_{{\text {OC}, \text {FBR}}}$) to relax the voltage-tolerance requirements. Fabricated in 0.18- $\mu \text{m}$ CMOS, the proposed 21-phase SPFCR PEH interface demonstrates a measured maximum output power improving rate (MOPIR) of up to 9.3 $\times $ with $V_{D}= 0.12$ V (6.5 $\times $ with $V_{D}= 0$ V) when compared with the conventional FBR interface over an equivalent FBR input power range ($P_{{\text {in, FBR}}}$) from 0.15 to 5.57 $\mu \text{W}$. [ABSTRACT FROM AUTHOR]

This article presents an algebraic series–parallel (ASP) topology for fully integrated switched-capacitor (SC) dc–dc boost converters with flexible fractional voltage conversion ratios (VCRs). By elaborating the output voltage (${V} _{\textrm {OUT}}$) expression into a specific algebraic form, the proposed ASP can achieve improvements on both the charge sharing and bottom-plate-parasitic losses while maintaining the high topology and fractional VCR flexibility of conventional two-dimensional series–parallel (2DSP) converters. The proposed method consists of a generic ASP topology framework with systematic parameter determination for a precise converter implementation, and can theoretically surpass the power-conversion efficiency (PCE) of 2DSP converters. Fabricated in 65-nm bulk CMOS, we designed a fully integrated ASP-based SC rational boost converter by cascading with the Dickson topology, with a total of seven rational VCRs to boost an input voltage of 0.25–1 V to a 1-V output. Delivering a maximum loading power of 20.4 mW, the chip prototype achieves a peak efficiency of 80% at a power density of 22.7 mW/mm2. [ABSTRACT FROM AUTHOR]

This brief presents the design methodology of an integrated KY dc–dc step-up converter with constant on-time (COT) control under discontinuous conduction mode (DCM) operation. The method improves the efficiency during the deep-light-load situation, and we analyze the design criteria of the flying capacitor as well as the COT controller of the KY converter under DCM. The simulation results verify that the design obtains higher conversion efficiency than the pulse width modulation controlled KY converter. The KY converter with COT control has been fabricated in 65-nm CMOS with a core area of 0.55 $\times $ 0.55 mm2. The circuit uses an off-chip inductor of 12 nH and an output capacitor of 4 nF. The converter operates with a current load ranging from 500 $\mu \text{A}$ to 10 mA with an output voltage ripple lower than 70 mV in the deep-light-load range. [ABSTRACT FROM AUTHOR]

We propose an algorithmic voltage-feed-in (AVFI) topology capable of systematic generation of any arbitrary buck–boost rational ratio with optimal conduction loss while achieving reduced topology-level parasitic loss among the state-of-the-art works. By disengaging the existing topology-level restrictions, we develop a cell-level implementation using the extracted Dickson cell (DSC) and charge-path-folding cell (QFC) to minimize the power-stage parasitic loss, exhibiting a Dickson-like switching pattern. The proposed partitionable main cell (MC) and auxiliary cell (AC) architecture achieves fined-grained voltage conversion ratio (FVCR) reconfiguration with optimal power cell utilization and reduced control complexity. Implemented in 65-nm bulk CMOS, the fully integrated switched-capacitor power converter (SCPC) using 10 MCs and 10 ACs executes a total of 24 VCRs (11 buck and 13 boost) with wide-range efficient buck–boost operations through the proposed reference-selective bootstrapping driver (RSBD). Based on the AVFI topology, the chip prototype reaches a measured peak efficiency of 84.1% at a power density of 13.4 mW/mm2 over a wide range of input (0.22–2.4 V) and output (0.85–1.2 V). [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated piezoelectric energy harvesting interface without external components. Instead of relying on bulky external inductors with high quality factor as in the conventional parallel-synchronized-switch harvesting-on-inductor (P-SSHI) approach, we propose a flipping-capacitor rectifier (FCR) topology to achieve voltage inversion of the piezoelectric energy harvester through a reconfigurable capacitor array. This fundamentally preserves a fully integrated solution without inductors while achieving a high-energy extraction capability. Measurement results from FCR1 using discrete components shows an output power enhancement of up to 3.4 \times , which is close to the theoretical prediction. We also fabricated a seven-phase FCR3 with four MIM capacitors and 21 switches using a 0.18- \mu \text{m} 1.8/3.3/6 V CMOS process, occupying an active area of ~1.7 mm2. Additionally, we implemented an active rectifier based on a common-gate comparator with phase alignment to ensure high-speed operation while minimizing the diode voltage drop. A phase generate-and-combine circuit eliminates redundant switching activities. Systematic optimization of the three main energy loss mechanisms during the finite flip time: 1) phase offset; 2) incomplete charge transfer; and 3) reduced conduction time, is also introduced. Measurement results show that the output power enhancement can reach up to 4.83 \times $ at an excitation frequency of 110 kHz. [ABSTRACT FROM AUTHOR]

This brief presents an ultra-low-power low-noise chopped capacitively coupled instrumentation amplifier (CCIA) that is suitable for neural recording applications. An active high-pass filter is embedded in the ripple reduction loop (RRL) to suppress the residual noise and relax the capacitor size. Multiple chopping is employed to further reduce the residual output ripple due to the RRL offsets. A dc servo loop (DSL) using a 14-nA pseudofeedback amplifier is proposed to achieve a subhertz high-pass corner while using only a 15-pF on-chip capacitor. The complete CCIA is implemented in a standard 0.18- \mu\textm CMOS process. It occupies an area of 0.23 mm2 (including the DSL) and consumes 1.7 \mu\textA from a 1.25-V supply, achieving a noise efficiency factor of 2.9 that compares favorably with the state of the art. [ABSTRACT FROM AUTHOR]

The die size of multistandard wireless transceivers in ultrascaled CMOS is dominated by the baseband low-pass filters (LPFs), which typically count on passive- $RC$ components to define the time constant. To break this area constraint, this paper revisits the active switched-capacitor (SC) LPF for its united benefits of clock-rate-defined bandwidth, accurate cutoff frequency, and small die size due to capacitor-ratio-based sizing and no spare elements. The key challenges of active-SC LPFs are the speed- and linearity-to-power tradeoffs, which are addressed by two circuit techniques: 1) switched-current assisting (SCA) and 2) precharging (PC). The SCA accelerates the charging speed of the integration capacitor, while the PC improves the linearity when charging the load capacitor. Three prototypes (first order, biquad, and fifth-order Butterworth) fabricated in a 65-nm CMOS process validate the feasibility of the proposed SCA and PC techniques. [ABSTRACT FROM AUTHOR]

This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-stage amplifier for wide capacitive load ( CL ) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of CL ; 2) no extra bias circuit and power, as the CM is embedded into the first stage of the amplifier, and 3) only one very small (subpicofarad) compensation capacitor improving the transient settling and area efficiency. Detailed analytical treatments of the amplifier offer the critical insights for device sizing and optimization. Fabricated in 0.18- \mu\m CMOS, the amplifier measures 3.06-MHz unity-gain frequency (UGF), 1.76- \V/\mu\s average slew rate (SR), and 74^\circ phase margin (PM) at 20-pF CL, and 0.22-MHz UGF, 0.049- \V/\mu\s SR, and 59.8^\circ PM at 15-nF CL. The die size is 0.0045 \mm^2, and power is 32.4\ \mu\W at 1.2 V. Competitive large- and small-signal figures of merit are achieved with respect to the state of the art. [ABSTRACT FROM PUBLISHER]

Analog-to-information converters (AICs) take advantage of the limited information bandwidth in high-frequency signals to improve the energy efficiency of front-end data converters. High-resolution image sensors often convey limited information due to the spatial redundancy between neighboring pixels. This paper proposes a mixed-signal AIC which compresses each nonoverlapping 4 × 4 pixel block in a 816 × 640 pixel prototype active-pixel sensor (APS) imager. It combines an energy-efficient charge-pump bit-image processor (BIP) with an area-efficient successive-approximation-register-single-slope (SAR-SS) hybrid analog-to-digital converter (ADC) via a charge-transfer-amplifier (CTA). The AIC is fully dynamic and consumes no static power. The ADC's capacitor array doubles as a computational device for parts of the compression algorithm which reduces its sampling rate by a factor of four. The compressed data contains direct edge information and can be decoded by a very simple receiver. The fabricated prototype consumes 12 pJ per pixel at 111 fps in the image compression mode and 48 pJ per pixel at 28.7 fps in raw data mode (9 b per pixel) under the same clock rate. To the best of our knowledge, this is the most energy-efficient compressive CMOS image sensor ever reported in the literature, thanks to the proposed AIC. [ABSTRACT FROM PUBLISHER]

Most biopotential readout front-ends rely on the g m-C lowpass filter (LPF) for forefront signal conditioning. A small g m realizes a large time constant (\tau= C / g m) suitable for ultra-low-cutoff filtering, saving both power and area. Yet, the noise and linearity can be compromised, given that each g m cell can involve one or several noisy and nonlinear V-I conversions originated from the active devices. This paper proposes the subthreshold-source-follower (SSF) Biquad as a prospective alternative. It features: 1) a very small number of active devices reducing the noise and nonlinearity footsteps; 2) No explicit feedback in differential implementation, and 3) extension of filter order by cascading. This paper presents an in-depth treatment of SSF Biquad in the nW-power regime, analyzing its power and area tradeoffs with gain, linearity and noise. A gain-compensation (GC) scheme addressing the gain-loss problem of NMOS-based SSF Biquad due to the body effect is also proposed. Two 100-Hz 4th-order Butterworth LPFs using the SSF Biquads with and without GC were fabricated in 0.35-\mu m CMOS. Measurement results show that the non-GC (GC) LPF can achieve a DC gain of -3.7 ~dB (0 dB), an input-referred noise of 36 \muV rms (29 \,\muV rms ), a HD3@60 Hz of -55.2 ~dB (- 60.7 ~dB) and a die size of 0.11 mm^2 (0.08 mm^2). Both LPFs draw 15 nW at 3 V. The achieved figure-of-merits (FoMs) are favorably comparable with the state-of-the-art. [ABSTRACT FROM PUBLISHER]

Recent theoretical and experimental findings suggest that biological olfactory systems utilize relative latencies or time-to-first spikes for fast odor recognition. These time-domain encoding methods exhibit reduced computational requirements and improved classification robustness. In this paper, we introduce a microcontroller-based electronic nose system using time-domain encoding schemes to achieve a power-efficient, compact, and robust gas identification system. A compact (4.5 cm\,\times\,5 cm\,\times\,2.2 cm) electronic nose, which is integrated with a tin–oxide gas-sensor array and capable of wireless communication with computers or mobile phones through Bluetooth, was implemented and characterized by using three different gases (ethanol, carbon monoxide, and hydrogen). During operation, the readout circuit digitizes the gas-sensor resistances into a concentration-independent spike timing pattern, which is unique for each individual gas. Both sensing and recognition operations have been successfully demonstrated in hardware. Two classification algorithms (rank order and spike distance) have been implemented. Both algorithms do not require any explicit knowledge of the gas concentration to achieve simplified training procedures, and exhibit comparable performances with conventional pattern-recognition algorithms while enabling hardware-friendly implementation. [ABSTRACT FROM PUBLISHER]