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This brief presents an analog front-end (AFE) specially developed for a water conductivity measurement system for water network management applications. Water conductivity is one of the best ways to detect a problem with the water in the network. In order to trigger an alarm it is only required to detect a 10% variation, which allows to simplify the system design. The proposed sensor uses four platinum micro-machined electrodes, where a 6 kHz signal is applied to the outer electrodes and a voltage signal is read in the inner ones. A programmable switched-capacitor (SC) bandpass filter is included in the analog-to-digital (A/D) channel to attenuate the interference from the 50 Hz power network, that shares the same environment with the water network, and to allow using a square wave signal to drive the sensor, thus simplifying the overall system. The resulting sine wave is digitized using a passive continuous-time (CT) 2nd order $\Delta\Sigma$ modulator. The output bitstream is decimated, using a sinc filter, and the RMS value of the voltage is calculated. The A/D acquisition channel was implemented in a 130 nm CMOS technology, using a supply voltage of 0.9 V and a clock frequency of 1 MHz (SC amplifier and SC bandpass filter) and 4 MHz ($\Delta \Sigma $ modulator). Measurement results show a SNDR of 44.4 dB for an input signal of 6 kHz and an amplitude of −41 dBV. The channel dissipates 386 $\mu \text{W}$ and occupies an area of 0.27 mm2. [ABSTRACT FROM AUTHOR]

This brief presents a programmable second-order bandpass switched-capacitor filter implemented for an Internet-of-Things water management sensor node. The filter circuit, which is based on the Sallen-Key topology, is implemented using a low-gain amplifier (<2), avoiding designing high-gain high-bandwidth opamps, which can be difficult to design in advanced CMOS technologies, due to the reduction of the supply voltage and of the intrinsic gain of the transistors. Without the high gain, the circuit becomes sensitive to the effects of parasitic capacitances, which have to be minimized and compensated during the design process. The filter circuit was designed and fabricated in a 130-nm CMOS technology, using a supply voltage of only 0.9 V, to reduce the power dissipation, and a clock frequency of 1 MHz. Measurement results show that the filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between −6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. In the default digital control code of the capacitor banks, the circuit has an IM3 of −66.5 dB. The total power consumption is 257 ${\boldsymbol \mu }\text{W}$. [ABSTRACT FROM AUTHOR]

This paper describes the design and experimental evaluation of a multibit Sigma-Delta (\Sigma \Delta) modulator (\Sigma \Delta M) with enhanced dynamic range (DR) through the use of nonlinear digital-to-analog converters (DACs) in the feedback paths. This nonlinearity imposes a trade-off between DR and distortion, which is well suited to the intended hearing aid application. The modulator proposed here uses a fully-differential self-biased amplifier and a 4-bit quantizer based on fully dynamic comparators employing MOS parametric pre-amplification to improve both energy and area efficiencies. A test chip was fabricated in a 130 nm digital CMOS technology, which includes the proposed modulator with nonlinear DACs and a modulator with conventional linear DACs, for comparison purposes. The measured results show that the \Sigma \Delta M using nonlinear DACs achieves an enhancement of the DR around 8.4 dB (to 91.4 dB). Power dissipation and silicon area are about the same for the two cases. The performance achieved is comparable to that of the best reported multibit \Sigma \Delta ADCs, with the advantage of occupying less silicon area (7.5 times lower area when compared with the most energy efficient \Sigma \Delta M). [ABSTRACT FROM PUBLISHER]