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In this work, a multilevel 42-sided polygonal space vector structure for suppression of lower order harmonics for open-end induction motor (OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an OEIM from either side. The main inverter fed with a single dc-link providing active power for motoring operation is switched at low switching frequency. The secondary inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the dc-link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures, are combined with multilevel inverter topology. This offers various advantages like multilevel operation with low inverter switching for the main power delivery inverter and harmonic suppression throughout the modulation range. The low switching frequency primary inverter generates harmonics of the order $6*k \pm 1$ , where $k = 1, 2, 3,{\ldots }$. The harmonics are suppressed by the capacitor-fed secondary inverter, which supplies only reactive power for suppression of lower order harmonics in motor phase voltage. Use of a single dc-link facilitates four-quadrant operation of the inverter. The proposed scheme is validated for steady-state and dynamic performance by experimental results. [ABSTRACT FROM AUTHOR]

Battery energy storage systems (BESS) based on modular multilevel converters (MMCs) allow battery packs to be integrated into the electrical grid in a modular fashion. Inherent to the operation of the MMC, the module's dc-link capacitor voltage experiences oscillations at grid frequency and its harmonics. This article investigates the close relation between this voltage oscillation and the battery current ripple. The precise capacitor energy requirements for various operations of BESS-MMC, which include arm/phase power balancing and state-of-charge balancing are analyzed in this article. Furthermore, this article also explores the relation between the controller design and the submodule's (SMs) capacitor sizing in terms of its energy requirements. Design guidelines for the SM level voltage control to attenuate battery ripple and detailed analysis for the capacitor energy requirement in each operating mode are presented. The control and capacitor sizing design are validated in real-time using embedded microprocessors in a Typhoon-based controller hardware-in-the-loop environment. [ABSTRACT FROM AUTHOR]

DC-link-based variable speed constant frequency (VSCF) ac power generating system is being considered as one of the popular power architectures in the new generation aircraft to provide backup power to the 115 V, 400 Hz aircraft loads. These systems directly convert the variable frequency output of the generator to the fixed frequency of 400 Hz using a voltage source inverter. These inverters use dc-link capacitors that are heavy and space consuming. In aircraft, the weight requirement is very critical; hence, minimizing the dc-link capacitance is one of the major research challenges to achieve high power density in the VSCF power converter. In this article, novel control strategies to minimize the dc-link capacitance of the ac–dc–ac VSCF power converter are presented. The proposed control strategies enable to achieve 95% reduction in dc-link capacitance value when compared with the conventional control strategy, while the control is robust enough to meet MIL-STD-704F transient specification at the inverter output. The proposed strategies are validated through controller hardware-in-loop testing of the VSCF system based on an 80 kVA brushless synchronous generator and a four-leg inverter. The transient and steady-state operation of the VSCF system with a 95% reduction in dc-link capacitance has been verified for rated power operation. [ABSTRACT FROM AUTHOR]

The increasing penetration of renewable energy resources (RESs) leads to a continuous displacement of synchronous generators. Since the grid integration of RESs is usually achieved through inertialess power converters, the system inertia reduces and the power system frequency stability is compromised. Consequently, unexpected generator tripping, load shedding, and even blackouts may occur and pose a great threat to the system normal operation. In view of these challenges, this article explores the possibility of providing the inertia support from power-electronics interfaced smart loads. Specifically, a transformerless electric spring topology and the associated control strategy have been developed to provide a substantial inertia support from the noncritical load. As compared with existing inertia enhancement techniques, the proposed solution is cost-effective without the need of additional energy storage units. The smart load inertia provision capability is quantitatively analyzed and experimentally verified on a laboratory-scale test. In the testing results, 40% and 18% reductions of the rate of change of frequency and the maximum frequency deviation are, respectively, observed with a 12% smart load penetration ratio. [ABSTRACT FROM AUTHOR]

Due to current sensor errors, tolerance of power switching devices, and asymmetry of PWM gating driving pulses, grid-connected inverters without isolation transformer usually have certain amount of dc components injected to the ac grid. Many efforts, such as using a blocking capacitor, a current dc component feedback control, and a voltage dc component feedback control have been introduced to try to suppress the dc injection to the grid. This paper proposes a novel control strategy of suppressing dc current injection to the grid for a three-phase inverter by accurately sensing the dc component of line voltages of three-phase inverter and adding a dc component control loop. A dc suppression control scheme is presented, and the suppression performance of the proposed dc rejection method is evaluated and compared with the traditional method. Finally, the control scheme is verified on a 20-kW three-phase grid-connected inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a novel harmonic suppression scheme for two-level inverter fed three-terminal induction motor drives using switched capacitive filter. Capacitor fed H-bridges used as filters are cascaded to conventional two-level inverter to eliminate fifth- and seventh-order harmonics for the full modulation range including a six-step operation. For the first time, two-level dodecagonal voltage space vector is implemented with single dc supply for three-terminal induction motor drive. Enabling the switched capacitive filtering at low-voltage domain and shifting the high frequency switching to the switched capacitive filter is shown. A uniform pulse width modulation technique is shown which charges and maintains the capacitor voltages while eliminating the fifth- and seventh-order harmonics for the full speed range. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included. [ABSTRACT FROM AUTHOR]

This paper proposes a new vector-based dead-time compensation method for three-level T-type converters. The origins and effects of the dead-time voltage errors are analyzed in detail for different switching commutations and load conditions. In order to eliminate the dead-time distortion in each phase, a dead-time error voltage vector is introduced to adjust the reference voltage vector depending on load current polarity. The proposed vector-based dead-time compensation scheme has several advantages. First, it can be applied to multilevel converters with any number of voltage levels using any modulation schemes. Second, the pulse loss issue which is common in conventional pulse-based compensation strategies can be eliminated. In addition, the pulse saturation can be mitigated by operating the converters in overmodulation regions. All of these advantages and effectiveness of the proposed vector-based dead-time compensation method are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

It is well known that single-phase pulse width modulation rectifiers have second-order harmonic currents and corresponding ripple voltages on the dc bus. The low-frequency harmonic current is normally filtered using a bulk capacitor in the bus, which results in low power density. However, pursuing high power density in converter design is a very important goal in the aerospace applications. This paper studies methods for reducing the energy storage capacitor for single-phase rectifiers. The minimum ripple energy storage requirement is derived independently of a specific topology. Based on the minimum ripple energy requirement, the feasibility of the active capacitor's reduction schemes is verified. Then, we propose a bidirectional buck–boost converter as the ripple energy storage circuit, which can effectively reduce the energy storage capacitance. The analysis and design are validated by simulation and experimental results. [ABSTRACT FROM AUTHOR]