Search

A five-level power factor correction topology with fault-diagnosis and fault-tolerant capabilities is proposed and analyzed. This structure is derived from the well-known three-level one-pole double-boost including double-stacked redundant and low-storage-energy flying capacitor cells. Two fault-diagnosis strategies are presented. The first one directly operates the monitoring of the voltages across the flying capacitors, detecting and localizing the faulty switch by means of two sensors. The second one is based on indirect voltage vector detection through only one sensor. Both of these strategies are analyzed and simulated with the efficient phase disposition pulsewidth modulation technique. The design and the most important features are highlighted owing to a digital control frame and a single-phase mock-up rated at 115 V/400 V, - 4 kW, and 2 \times 31 kHz. The presented results also offer a dedicated strategy permitting an optimized real-time reconfiguration in postfault operation. [ABSTRACT FROM PUBLISHER]

This paper deals with a hybrid fault-tolerant converter topology. It is performed through the connection of a classical three-phase three-level neutral-point-clamped (3L-NPC) converter with a fourth three-level flying capacitor (3L-FC) leg. The 3L-FC leg actively balances the 3L-NPC neutral-point voltage. For normal operation mode, this paper proposes a mathematical design of the filter needed to connect these two different topologies. Experimentally, and thanks to the already existing decoupling capacitors of the 3L-NPC converter, this filter requires the addition of only one low size inductance. When one fault of the power switch of the 3L-NPC occurs, this paper proposes a hardware reconfiguration technique based on only two fuses and one thyristor per leg allows a safe postfault operation recovery. This is achieved thanks to a simple fault-detection method and a new technique that combines fault leg isolation and corresponding phase postfault connection to the neutral point. Also, a dedicated field-programmable gate array (FPGA)-based control of the reconfigured converter is synthetized to ensure power system availability under fault operation mode. The converter fault-tolerant capabilities are addressed through simulation results and original overall experimental validations of the fault detection and isolation and the postfault operation steps, carried out on a 15-kW prototype converter. [ABSTRACT FROM AUTHOR]

Presents a study that examined the switching faults and safe control of an auxiliary resonant commutated pole (ARCP) multicell flying capacitor inverter. General properties and operation of ARCP two levels inverter leg; Simulation of the flying capacitor voltages waveforms in steady state; Experimental switching fault.

This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high dv/dt of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the dv/dt with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the dv/dt sequence of the switching transients. Hence, the dv/dt and di/dt can be actively controlled separately, and the tradeoff between the dv/dt and EON switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for dv/dt active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak dv/dt from –175 to –120 V/ns for the 400 V application. [ABSTRACT FROM AUTHOR]