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This study addresses the calculation of current total harmonic distortion (THD) for three-phase (3P) pulse-width modulation (PWM) inverters. First, it demonstrates how an analytical approach to PWM current ripple normalised mean square (NMS) calculation introduced in the late 1980s for a two-level (2L) inverter can be used for current THD evaluation. Second, it is shown how to evaluate current THD for a three-level (3L) 3P inverter using the current ripple NMS concept. Though considered is a 3P cascaded inverter with one H-bridge per phase, the results are applicable to popular 3L neutral point clamped (T-type) and flying capacitor inverters. [ABSTRACT FROM AUTHOR]

This brief addresses inverting switched capacitor converter (SCC) for driving the white light emitting diodes (WLEDs). The various voltage conversion ratios (VCRs) are selected to control the WLEDs blacklights, which helps to save the battery life. The major contribution are developing maximum VCRs for power converter integrated circuits (ICs) and equivalent resistance (Req) accurate calculation which includes all conduction and ohmic losses. Furthermore, inverting SCC (ISCC) experimental results are obtained from prototype model. Accurate Req analyses validates the accuracy of proposed topology. It is designed for low voltage of 10 mV to 0.1 V and it provides the output voltage of −100 mV to −0.5 V. Finally, the novelty of accurate Req calculation in this brief is that the calculation results are verified with experimental ones, particularly, at the transition region (between slow switching limit and fast switching limit). On the other hand, calculation, simulation and experimental results perfectly coincide with each other. Accurate equivalent resistance calculation and average current calculation are compared and some of the recent publications providing the merits of the proposed converter are explained. [ABSTRACT FROM AUTHOR]

Here, accurate transresistance calculations for the coupled case and mathematical modelling are provided for dual input–output switched capacitor converter (SCC). This converter offers two different output voltages and produces 36 voltage conversion ratios. The dual input–output SCC is portable and operates by considering either sources or the combination of both Vs1 and Vs2 as input sources. The proposed dual input–output SCC has the ability to vary 54 voltage ratios. An efficient low‐power SCC is designed for an input voltage range of 1.5–5 V and it gives dual‐output voltages of 1–10 V. The proposed converter can operate in both buck and boost modes. The SCC has high drive capability of load current in the range of 10 µA to 100 mA that is adjusted by varying the operating frequency. The accurate equivalent resistance for both coupled and decoupled load cases is found and validated. The results are verified through PSIM simulations and validated experimentally. The mathematical, simulation, and experimental results give excellent proof for proposing the newly designed converter for applications requiring large conversion ratios eliminating inductors. [ABSTRACT FROM AUTHOR]

Reported capacitor average natural voltage balancing dynamics analysis methods are mostly based on frequency-domain Fourier transformations that involve infinite series. Therefore, these methods require high mathematical skills, are not truly analytical and difficult to use in engineering practise. This study suggests a time-domain power averaging-based approach to the analysis of a multilevel DC–DC flying capacitor converter (or, more generally, switched capacitive converter) aperiodic (non-oscillating) average voltage balancing dynamics. Simple analytical solutions are illustrated by single and dual capacitor converter examples that include pure resistive load and balance booster circuit. Theoretical results are supported by simulations and experimental verification. [ABSTRACT FROM AUTHOR]

Presents a comments on the paper, "Nearest and non-nearest three vector modulations of NPCI using two-level space vector diagram - a novel approach," (Babu, N. and Agarwal, P.), IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1999-2009, 2013. [ABSTRACT FROM AUTHOR]

This paper presents the implementation of a maximum power point tracking (MPPT) algorithm in a multilevel three-phase photovoltaic (PV) system using the ripple correlation control (RCC) method. Basically, RCC adopts the inherent oscillations of PV current and voltage as perturbation, and it has been predominantly used for single-phase configurations, where the oscillations correspond to the 2nd order harmonics. The implementation of an RCC-MPPT algorithm in a three-phase system has not been presented yet in the literature. In this paper, the considered three-phase three-level converter is a three-level flying capacitor (FC) inverter. The proffered RCC method uses the 3rd harmonic components of PV current and voltage for the estimation of the voltage derivative of the power dPpv/dVpv (or current, dIpv/dVpv), compelling the PV array to operate at or very close to the maximum power point. The analysis and calculation of the low-frequency PV current and voltage ripple harmonic components in the three-phase flying capacitor inverter is presented first, with reference to centered carrier-based three-level PWM. The whole grid-connected PV generation scheme has been implemented by MATLAB/Simulink, and detailed numerical simulations verified the effectiveness of the control method in both steady-state and dynamic conditions, emulating different sun irradiance transients. [ABSTRACT FROM AUTHOR]

This paper presents a novel optimization technique for Switched Capacitor Converters (SCCs). The optimization focuses on minimizing the SCC equivalent resistance by adjusting MOSFET widths and switching duty cycles. The optimized SCC parameters are obtained from numerical optimization with constant total transistor width and switching period constraints. The transistor carrier mobilities and gate-to-source voltages are accounted during the optimization. A Fibonacci SCC with two flying capacitors is used as an example and is simulated in a 65 ​nm low-power process. By comparing SCC parameters before and after the optimization, we obtain certain performance improvements. Particularly, at a switching frequency of 10 MHz and 50 Ω load, the optimized design shows improvement in average and minimum output voltage parameters by 2.5% and 4.1%, respectively, which are caused by 20.6% reduction of the equivalent resistance. The output voltage ripple is also decreased by 22.4%. By sweeping the duty cycle and transistor widths in simulation, the optimized parameters show nearly the best performance. [ABSTRACT FROM AUTHOR]