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A new architecture is proposed which reduces the power consumption and capacitor area in successive approximation register (SAR) analogue-to-digital converters (ADCs). Two identical capacitor-splitting capacitor arrays are used in a two-step process for quantisation, and this significantly reduces the switching power and capacitor area. [ABSTRACT FROM AUTHOR]

A low-power parasitic-insensitive switched-capacitor (SC) integrator is proposed for ΔΣ ADCs. Compared to the conventional SC integrator, the new one achieves much lower power dissipation for the same sampling noise specification. A cancellation technique is used to reduce the nonlinearity of the integrator. An effective ΔΣ ADC topology is described which can incorporate the new integrator. Simulation shows that high linearity can be achieved by the new integrator, while consuming very low power. [ABSTRACT FROM AUTHOR]

A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analogue-to-digital converters (SAR ADCs). Two split-junction binary-weighted capacitor arrays are used in a coarse/fine quantisation scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC. [ABSTRACT FROM AUTHOR]

In this Letter, an opamp-free noise shaping successive-approximation register (SAR) ADC is proposed. Third-order noise shaping is achieved by implementing a second-order passive filter and a passive error feedback topology. In the proposed scheme, the SAR error signals (including quantisation noise, comparator thermal noise, DAC thermal noise and settling error) are subjected to third-order noise shaping. Therefore, the thermal noise specifications of the comparator can be relaxed. Also, since no active element is used, the proposed scheme achieves a higher power efficiency than earlier SAR ADCs. [ABSTRACT FROM AUTHOR]

A simple and highly efficient successive-approximation registers (SAR) ADC realisation is proposed. It requires an opamp, a comparator and only three equal-valued capacitors. The proposed scheme is insensitive to the capacitor parasitics, and has a small capacitance spread. With an oversampled scheme, it also allows noise-shaping the remaining quantisation error. It is well-suited for low-frequency instrumentation and measurement applications, and for use in extended-counting ADCs. [ABSTRACT FROM AUTHOR]

A high-precision switched-capacitor integrator using a low-gain opamp is proposed. The circuit contains a main signal path and a predictive signal path which makes the correlated double sampling more effective. The proposed integrator was simulated using SPICE parameters for a 180 nm CMOS process with a supply voltage of 1.2 V. The circuit exhibited much lower harmonic distortion than those described in earlier works. [ABSTRACT FROM AUTHOR]

The first-order noise coupling scheme proposed earlier is generalised to the realisation of higher-order enhancement. It is also extended to single-stage ΔΣ loops, and to split structures with self-enhancement. The advantages and limitations of these new ΔΣ architectures are compared with those of conventional single-stage and cascade ΔΣ structures. As demonstrated by an example, they exhibit improved stability and robustness under practical fabrication conditions. [ABSTRACT FROM AUTHOR]