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This paper presents the current control design procedure of a single-phase grid-tied five-level packed U-cell inverter (PUC5) with an LCL output filter. The PUC5 inverter is used as an interface of renewable energy sources, such as solar applications. The LCL filter is calculated according to the grid-tied operation and converter ratings. An optimal controller, based on a linear quadratic regulator with integral action, is designed to inject a sinusoidal current with low harmonic distortion at unity power factor. For that design, the PUC5 inverter is modelled in the D–Q frame. The sensorless voltage control is incorporated into the switching technique to balance the PUC5 capacitor voltage and generate a five-level waveform at the output. Experimental tests are performed on a laboratory benchmark to confirm the theoretical design. The results prove the efficiency and accuracy of the adopted control strategy in a steady state and under transients of grid current, grid inductance, ac and dc voltage amplitudes. [ABSTRACT FROM AUTHOR]

In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]

In this letter, the five-level packed U-cell (PUC5) inverter is reconfigured with two identical dc links operating as an active power filter (APF). Generally, the peak voltage of an APF should be greater than the ac voltage at the point-of-common coupling (PCC) to ensure the boost operation of the converter in order to inject harmonic current into the system effectively; therefore, full compensation can be obtained. The proposed modified PUC5 (MPUC5) converter has two equally regulated separated dc links, which can operate at no load condition useful for APF application. Those divided dc terminals amplitudes are added at the input of the MPUC5 converter to generate a boosted voltage that is higher than the PCC voltage. Consequently, the reduced dc-links voltages are achieved since they do not individually need to be higher than the PCC voltage due to the mentioned fact that their summation has to be higher than PCC voltage. The voltage balancing unit is integrated into the modulation technique to be decoupled from the APF controller. The proposed APF is practically tested to validate its good dynamic performance in harmonic elimination, ac-side power factor correction, reactive power compensation, and power quality improvement. [ABSTRACT FROM AUTHOR]

This paper presents a closed-loop space vector modulation (SVM)-based sliding mode controller (SMC) for a three-level grid-connected neutral point clamped (3L-NPC) inverter. The nonlinear SMC based on Gao's reaching law has been designed to control the grid current and inject desired amount of active and reactive power into the network. Due to using single dc source at the NPC inverter dc bus, neutral point voltage is controlled through redundant switching states and instantaneous dc voltage feedback integrated into SVM technique. Meanwhile, there is no external voltage controller involved, thus no associated fine tuning issues are existed. The performance of the proposed hybrid controller to inject a desired active/reactive power to the grid is investigated through external perturbations such as change in the line current amplitude/phase shift, ac voltage fluctuation, as well as dc voltage variation. Full converter state-space model was developed and simulated. Experimental results are provided to verify the fast dynamic performance, low content of line current THD%, and good voltage balancing of dc bus capacitors of the NPC inverter. [ABSTRACT FROM AUTHOR]

A multilevel boost power factor correction (PFC) rectifier is presented in this paper controlled by cascaded controller and multicarrier pulse width modulation technique. The presented topology has less active semiconductor switches compared to similar ones reducing the number of required gate drives that would shrink the manufactured box significantly. A simple controller has been implemented on the studied converter to generate a constant voltage at the output while generating a five-level voltage waveform at the input without connecting the load to the neutral point of the dc bus capacitors. Multicarrier pulse-width modulation technique has been used to produce switching pulses from control signal at a fixed switching frequency. Multilevel voltage waveform harmonics has been analyzed comprehensively which affects the harmonic contents of input current and the size of required filters directly. Full experimental results confirm the good dynamic performance of the proposed five-level PFC boost rectifier in delivering power from ac grid to the dc loads while correcting the power factor at the ac side as well as reducing the current harmonics remarkably. [ABSTRACT FROM PUBLISHER]

This paper presents a new family of buck type power factor corrector rectifiers that operates in continuous-conduction mode (CCM) and generates a multilevel voltage waveform at the input. Due to CCM operation, commonly used ac-side capacitive filter and dc-side inductive filter are removed from the proposed modified packed U-cell rectifier structure. Dual dc output terminals are provided to have a five-level voltage waveform at the input points of the rectifier where it is supplied by a grid via a line inductor. Producing different voltage levels reduces the voltage harmonics which affects the grid current harmonic contents directly. Low switching frequency of the proposed rectifier is a distinguished characteristic among other buck type rectifiers that reduces switching losses and any high switching frequency related issues, significantly. The proposed transformerless, reduced filter, and multilevel rectifier topology has been investigated experimentally to validate the good dynamic performance in generating and regulating dual 125-V dc outputs terminals as telecommunication boards feeders or industrial battery chargers under various situation including change in the loads and change in the main grid voltage amplitude. [ABSTRACT FROM PUBLISHER]

In this paper, a new cascaded nonlinear controller has been designed and implemented on the packed U-cell (PUC) seven-level inverter. The proposed controller has been designed based on a simplified model of PUC inverter and consists of a voltage controller as an outer loop and a current controller as an inner loop. The outer loop regulates the PUC inverter capacitor voltage as the second dc bus. The inner loop is in charge of controlling the flowing current, which is also used to charge and discharge that capacitor. The main goal of the whole system is to keep the dc capacitor voltage at a certain level results in generating a smooth and quasi-sine-wave seven-level voltage waveform at the output of the inverter with low switching frequency. The proposed controller performance is verified through experimental tests. Practical results prove the good dynamic performance of the controller in fixing the PUC capacitor voltage for various and variable load conditions and yet generating low-harmonic seven-level voltage waveform to deliver power to the loads. Operation as an uninterruptible power supply (UPS) or ac loads interface for photovoltaic energy conversion applications is targeted. [ABSTRACT FROM AUTHOR]

In this paper, a model-predictive control (MPC) has been designed and implemented on the packed U-cell (PUC) inverter, which has one isolated dc source and one capacitor as an auxiliary dc link. The MPC is designed to regulate the capacitor voltage at the desired magnitude to have seven voltage levels at the output of the inverter. Since grid-connected application is targeted by this application, the inverter should be capable of supplying requested amount of active and reactive power at the point of common coupling (PCC) as well. Therefore, MPC should also consider the line-current control to monitor the exchange of reactive power with the grid while injecting appropriate active power at low total harmonic distortion (THD). Various experimental tests including change in dc-source voltage, active power variation, and operation at different power factor (PF) have been performed on a laboratory prototype to validate the good performance obtained by the proposed MPC. The dynamic performance of the controller during sudden changes in dc capacitor voltage, supply current, and PF demonstrates the fast and accurate response and the superior operation of the proposed controller. [ABSTRACT FROM PUBLISHER]

In this paper, selective harmonic mitigation (SHM) and selective harmonic elimination (SHE) modulation techniques have been combined to produce appropriate pulses for a four-leg three-level neutral point clamped (NPC) inverter. In the proposed hybrid method, the SHM technique is applied to phase legs in order to mitigate non-triplen harmonics (fifth, seventh, $\ldots$) , and the fourth leg is controlled by the SHE principle to eliminate important low-order triplen harmonics (third, ninth, $\ldots$) completely. In this context, it is demonstrated that using SHM instead of an SHE modulator for phase legs leads to a reduced vast range of harmonic orders in the NPC output voltage, significantly. Moreover, it is proved that the presented hybrid switching technique has the ability of dc-bus capacitor voltage balancing, inherently. Furthermore, analyses are performed to calculate the dc-bus capacitances accurately to show 5% voltage ripple acceptably. Simulation and experimental results validate a good dynamic performance of the proposed hybrid modulation technique in firing the NPC inverter switches to generate low-harmonic voltage waveforms supplying balanced and unbalanced loads while balancing the dc capacitor voltages in a four-wire network with small dc-link capacitors. [ABSTRACT FROM PUBLISHER]

Multilevel inverters (MLIs) are widely employed in high power and high voltage applications due to their advantages like better power quality and lower voltage stress across power switches compared to the traditional two-level inverter. However, the utilization of higher number of power semiconductor devices and capacitors results in less reliability. In this regard, a fault-tolerant MLI (FTMLI) with asymmetrical source configuration is developed which can tolerate the open-circuit and short-circuit switch failures (single and multiple switch faults). The proposed topology preserves the output power and balances the capacitor's voltage under pre and postfault conditions. Further, a new switching scheme is proposed to reduce the ripple content in the capacitor's voltage. Further, under postfault operation uses less number of conducting switches resulting in a better efficiency. The proposed FTMLI generates a higher number of voltage levels with less number of component counts when compared with recently proposed topologies. Moreover, this comparative study reveals the prevalence of the proposed converter in the recent literature. The conducted experimental test proves the effectiveness and fault-tolerant feature of the proposed topology. [ABSTRACT FROM AUTHOR]