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Multivoltage domains are urgently needed in modern system on chips (SoCs), while existing solutions such as switched dc−dc converter, switched capacitor converter, and low-dropout regulator (LDO) do not generate multivoltage domains conveniently and inexpensively. This article presents a highly efficient fully integrated power management strategy to provide the multiple voltage domains. The proposed architecture stacks a main LDO and several auxiliary push−pull regulators (APPRs) to generate multiple voltages for various loads in one SoC chip. The APPR regulates the load current by either absorbing or providing the additional current, which stabilizes the output voltages, increases the power supply rejection (PSR) and decreases the cross-regulation. A prototype with two output terminals is implemented with a standard 0.18-μm CMOS technology. The whole system achieves high power efficiency of 96.5% and high PSR of −62 and −142 dB for upper and lower outputs, respectively. The chip area is 980 μm × 500 μm and the total quiescent current is 239 μA. In addition, all off-chip components are eliminated, which is favorable for monolithic realization. The reduced system cost and the reduced electromagnetic interference also simplify the power management significantly, which helps to enable low-power and compact SoCs. [ABSTRACT FROM AUTHOR]

Soft-start strategy is very important for boost converters to guarantee the stability of the output voltage. However, previous methods may cause large initial inrush current and long output voltage settling time. In this paper, a variable ramp-slope with predefined voltage (VRSPV) soft-start strategy is proposed. As a result, one branch of the initial inrush current is successfully eliminated and the output settling time of the boost converter is shortened by using the variable slope soft-start voltage. Also, an adaptive inrush current suppressing (AICS) technique is designed. The series resistance of the output capacitor is adaptively regulated by AICS technique to further suppress the initial inrush current. Finally, the VRSPV strategy and AICS technique are combined and implemented in a voltage-mode boost converter. The measurement results show that the peak initial inrush current and settling time are decreased by 60% and 40%, respectively. The output voltage of the boost converter increases smoothly during the soft-start period and finally achieves stability. The proposed method of combining VRSPV strategy and AICS technique is very suitable to be integrated on a chip to save the printed circuit board area and cost. [ABSTRACT FROM AUTHOR]