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This study presents a new scalable mathematical approach for designing compressors with any arbitrary number of inputs using multi‐input threshold gates, behaving as exclusive‐OR (XOR). This study relates the theoretical concept to hardware implementation. The methodology is exploited for 3:2, 7:3, and 15:4 compressors, and then implemented by using input capacitors (or resistors) and threshold detectors. The transistor‐level realisation of 3:2 and 7:3 compressors is simulated by using Synopsys HSPICE and 32 nm Carbon Nanotube Field Effect Transistors technology. The proposed methodology benefits from the parallel operation of threshold detectors. Therefore, by increasing the number of inputs, the delay parameter does not increase dramatically. The layout views are also provided in order to be able to compare area for the 3:2 compressors with both capacitor and resistor networks. [ABSTRACT FROM AUTHOR]