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Atmospheric pressure plasma deposition (APPD) of poly(ethylene oxide) (PEO)‐like antifouling coatings provides an attractive way to reduce biofouling for reliable biosensor operation. Cold atmospheric pressure plasma jets are designed to operate in open air. This paper demonstrates the impact of open‐air processing on the composition and properties of PEO‐like coatings by APPD with vinyl ether precursors. The open‐air environment inhibits polymerization as indicated by low deposition rates, oxygen incorporation in the coatings, and instability of the coatings in water. The composition and stability of the coatings improve by appropriate nozzle design and by deposition in an environment with lower air content. The resulting PEO‐like coatings are stable and antifouling for an antibody solution and inhibit adhesion of human fibroblast cells. [ABSTRACT FROM AUTHOR]

Area‐selective deposition (ASD) is a bottom‐up technique that provides numerous opportunities for nanoelectronic device fabrication. For example, advanced nano‐interconnect structures with barrierless metals like Ru in the contact holes can be created by Ru ASD with the bottom metals as growth surfaces and dielectrics as non‐growth surfaces. This work investigates Ru ASD by chemical vapor deposition (CVD) on industrially relevant substrates and nanopatterns and reveals how selectivity and growth rate are modulated by the CVD conditions and type of nanopattern. For low‐k dielectric/Cu substrate combinations, the selectivity reverses from metal‐on‐metal to metal‐on‐dielectric upon only changing the CVD co‐reagent from H2 to NH3. In contrast, NH3 is the preferred co‐reagent for SiO2‐TiN line patterns with critical dimension (CD) of 40 nm due to the more favorable adsorption and diffusion kinetics that cause growth rate and selectivity enhancement. Consistent with a diffusion‐mediated mechanism, the growth rate enhances even more for Ru CVD on nanoscale contact holes with CD of 10.5 nm, becoming 2.4 times higher as compared to unpatterned substrates. Thus, the ASD process changes drastically when pattern dimensions reach the nanoscale. The reported insights facilitate rational design of metal ASD processes for multiple applications in nanofabrication. [ABSTRACT FROM AUTHOR]

Nanoelectronics holds significant promise for two-dimensional (2D) semiconducting transition metal dichalcogenide (TMD) applications. On a polycrystalline WS2 monolayer created by metal-organic chemical vapor deposition (MOCVD) at 950 °C, we studied the nucleation, growth, and development of Al2O3 atomic layer deposition (ALD) on a SiO2/Si substrate. In this investigation, we used various complementary characterization methods, such as Raman spectroscopy, elastic recoil detection, atomic force microscopy, and time-of-flight secondary ion mass spectrometry, to understand thoroughly the intrinsic reactivity of WS2. Strong peak intensity changes at the interfaces in the Raman line scans of the SiO2/Si patterns suggest extremely crystalline WS2. After multiple ALD cycles, triangular WS2 crystals were decorated to provide a two-dimensional growth mode with a great selectivity for grain boundaries and step edges. The results of this work can be used for further exploration of the TMD monolayer structure and properties, which is essential for tailoring 2D materials for a specific application in devices. [ABSTRACT FROM AUTHOR]

The presence of deep levels in a silicon-oxygen (Si-O) superlattice (SL) deposited on p-type silicon substrates has been investigated by deep-level transient spectroscopy (DLTS) on thermally evaporated Cr Schottky barriers (SBs). The SLs have been fabricated with different thicknesses of the silicon interlayers, formed by chemical vapor deposition. It is shown that a broad band of hole traps is present near the surface of the SB, which is associated with the SL. In addition, the activation energy corresponding with the peak maximum shifts to higher values with respect to the valence band and gives rise to a higher trap concentration with increasing silicon interlayer thickness. It is proposed that these states are associated with the structural defects found in similar SL structures, that is, with the epitaxial quality and not with the SiO bonds in the atomic layers. The change in the DLT-spectra with silicon thickness could be related with the transformation of the structural defects from small self-interstitial clusters to stacking faults. [ABSTRACT FROM AUTHOR]

Abstract: Band engineered Si/O superlattices are promising channel materials for ultimately scaled complementary metal oxide semiconductor devices. Theoretical calculations have indicated that insertion of O monolayers into Si lattice creates anisotropy in the Si band structure with an enhanced carrier mobility in the channel direction. However, the experimental demonstration of such superlattices is not straightforward, as it requires processes for the deposition of a monolayer of O on Si, and to continue the Si epitaxy thereon. In this work, we investigate processes for the fabrication of Si/O superlattices using the chemical vapor deposition technique. Ozone is used for the O deposition with control of the deposited O content at the monolayer level. The SiH4 based Si deposition is performed at low temperatures (500°C–550°C) in order to obtain a confined O monolayer in the Si superlattice. Si deposited on O layer of 1.2 O monolayers is completely amorphous. This indicates that this O layer is extremely uniform as it prevents any epitaxial ordering with the substrate. Reducing the O content to 0.9 O monolayers in combination with a slower Si deposition favors epitaxial ordering of Si on O/Si. Finally a defect free Si epitaxy is demonstrated on the O monolayer. Such ordering of epitaxial Si on the O layer provides a promising outlook for the growth of superlattices. [Copyright &y& Elsevier]

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Å, a leakage current of 1.5 A/cm² at VG = 1 V, a peak mobility of 190 cm²/V · s, and a drive-current of 815 μA/μm at an OFF-state current of 0.1 μA/μm for VDD = 1.2 V. Identical gate stacks processed with a 1000-°C spike anneal have a higher peak mobility at 275 cm²/V · s, but a 5-Å higher EOT and a reduced drive current at 610 μA/μm. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 °C) for a ten-year lifetime, whereas positive-bias temperature-instability :measurements indicate a sufficient lifetime for operating voltages below 0.75 V. [ABSTRACT FROM AUTHOR]

The epitaxial growth of Si layers on Si substrates in the presence of O atoms is generally considered a challenge, as O atoms degrade the epitaxial quality by generating defects. Here, we investigate the growth mechanisms for Si epitaxy on O atomic layers (ALs) with different O-contents and structures. O ALs are deposited by ozone (O 3 ) or oxygen (O 2 ) exposure on H-terminated Si at 50 °C and 300 °C respectively. Epitaxial Si is deposited by chemical vapor deposition using silane (SiH 4 ) at 500 °C. After O 3 exposure, the O atoms are uniformly distributed in Si-Si dimer/back bonds. This O layer still allows epitaxial seeding of Si. The epitaxial quality is enhanced by lowering the surface distortions due to O atoms and by decreasing the arrival rate of SiH 4 reactants, allowing more time for surface diffusion. After O 2 exposure, the O atoms are present in the form of SiO x clusters. Regions of hydrogen-terminated Si remain present between the SiO x clusters. The epitaxial seeding of Si in these structures is realized on H-Si regions, and an epitaxial layer grows by a lateral overgrowth mechanism. A breakdown in the epitaxial ordering occurs at a critical Si thickness, presumably by accumulation of surface roughness. [ABSTRACT FROM AUTHOR]