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The authors discuss several important circuits for fiber-optic transmission, implemented in an advanced silicon bipolar integrated circuit technology. Specifically, the authors discuss the design considerations and measured performance of a 2:1 multiplexer, front end receiver, limiting amplifier, and decision circuit IC. Also discussed are three hybrid circuit modules: a 2:1 multiplexer, 1:2 demultiplexer, and parallel processing decision circuit. These ICs and hybrid circuit modules operate at multi-Gb/s data rates. The performance of these ICs indicates that advanced silicon bipolar integrated circuits with their high speed, functionality and low cost potential could play an important role in alleviating the electronic bottleneck in future multigigabit optical communication systems. >

A cell-based array is described which is intended primarily for mixed-signal receiver-on-a-chip (ROC) applications. The array is implemented in a silicon bipolar process with peak f/sub T/ and f/sub max/ of 14 GHz and 20 GHz, respectively. The process has two-level Au metal, 2- mu m emitter-base pitch interdigitated devices, polysilicon thin-film resistors, and 2- mu m-thick field oxide for minimal wiring parasitics. The basic RF and digital subsystem blocks available on the array are illustrated. The 1.8*1.8 mm/sup 2/ array is intended primarily for receiver applications up to 4 GHz, but can also implement many transmit functions for systems up to 2 GHz with separate external power amplifiers. An example application for a Global Positioning System satellite receiver is shown by an architecture where most of the RF and phase-locked loop components have been integrated on the array. >

State-of-the-art 0.15- mu m-gate PHEMT (pseudomorphic high-electron-mobility transistor) devices, self-biasing current sources, source follower interstage, resistive feedback, and on-chip matching have been used to make an unique MMIC (monolithic microwave integrated circuit) LNA (low noise amplifier). Typical gain of 21 dB, VSWR (voltage standing wave ratio) of 2:1, and P-1-dB output power of 7 dBm have been measured. The die area is small (0.40 mm/sup 2/) and is compatible with surface mount packages. DC power requirements are low, consuming only 14 mA from a single +5-V supply. This MMIC LNA has the best combination of noise figure, gain. low current, match, wide bandwidth, and low cost of any advertised or published product known to the authors to date. >

The authors have designed and implemented a submicron silicon bipolar parallel processing master-slave D-type flip-flop decision circuit, operating at data rates as high as 11 Gb/s. This is the fastest reported decision circuit for silicon bipolar technology. The ICs used in the hybrid circuit were fabricated using a 0.6 micron, non-polysilicon emitter technology, and mounted in a package employing coplanar waveguides. The performance of the IC indicates that silicon bipolar technology, with its relatively mature process and proven reliability as well as its low-cost potential, could play an important role in high-speed lightwave communication systems with data rates of up to 10 Gb/s or higher. >

Vertical pnp transistors have been fabricated using a four mask, low cost quasi-selfaligned process with submicrometre feature sizes. The resulting monocrystalline emitter devices achieve ft greater than 9 GHz and fmax greater than 15 GHz with BVceo greater than 13 V. These discrete pnps were used successfully as active loads for a monolithic npn opamp to achieve a gain-bandwidth product of 4.4 GHz.

The design and implementation of a submicron-silicon bipolar parallel processing master-slave D-type flip-flop decision circuit, operating at data rates as high as 11 Gbit/s is described. This is the fastest reported decision circuit for silicon bipolar technology. The ICs used in the hybrid circuit were fabricated using a 0.6 μm, non-polysilicon emitter technology, and mounted in a package employing coplanar waveguides.