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We measure the Casimir force gradient between silicon surfaces with nanoscale, rectangular corrugations and a gold sphere attached to a micromechanical torsional oscillator. By comparing the force gradients on the corrugated surfaces to that on a smooth, flat surface of the same material, we demonstrate that the Casimir force deviates from the value expected from the pairwise additive approximation and the proximity force approximation. The observed deviation qualitatively agrees with calculations that take into account the interplay between finite conductivity and geometry effects. However, the agreement is not exact, possibly due to uncertainties in the optical properties of the silicon substrate.

An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated.

A new approach is presented for fabricating monolithic crystalline silicon tilting-mirror microoptoelectromechanical systems (MOEMS) devices. The activation electrodes, etched from a thick silicon layer deposited over insulating oxide onto the top surface of a silicon-on-insulator (SOI) wafer, are displaced from the mirrors and interact with these tilting elements via electrostatic fringing fields. In contrast to the more usual parallel-plate activation, the rotation angle saturates at high voltages. This paper discusses concept, design, and processing, and also compares modeling and measured performance of a specific 9/spl deg/ tilt range device array.

The exponential growth of the silicon industry can be attributed to that fact that silicon has a native oxide that is silicon dioxide. With SiO 2 soon approaching its fundamental limit, we must find an alternate to SiO 2 or a new switch to replace MOSFETs. In this paper we focus on the leading alternate gate dielectrics. We first discuss the selection criteria for alternate gate dielectrics and why it is important to have an amorphous gate dielectric. SiO 2 and aluminum oxide remain amorphous at very high temperatures. For dielectrics with K >15 and gate power 2 , it may be necessary to stabilize the amorphous phase of metal oxides by adding Al or Si to the oxide, thus forming multi-component dielectrics such as aluminates. We then benchmark aluminates with aluminum oxide and silicon dioxide.

A copper/air-gap interconnection structure using a sacrificial polymer and SiO/sub 2/ in a damascene process has been demonstrated. The air-gap occupies the entire intralevel volume with fully densified SiO/sub 2/ as the planar interlevel dielectric. The copper was deposited by physical vapor deposition and planarized by chemical-mechanical planarization. The Ta/Cu barrier/seed layer was deposited by physical vapor deposition; the bulk copper was electrochemically deposited. The resulting structure has an effective intralevel dielectric constant of 2.19.

We report measurements of the Casimir force between a gold sphere and a silicon surface with an array of nanoscale, rectangular corrugations using a micromechanical torsional oscillator. At distance between 150 nm and 500 nm, the measured force shows significant deviations from the pairwise additive formulism, demonstrating the strong dependence of the Casimir force on the shape of the interacting bodies. The observed deviation, however, is smaller than the calculated values for perfectly conducting surfaces, possibly due to the interplay between finite conductivity and geometry effects., Comment: 5 pages, 3 figures

We demonstrate for the first time that chemical oxide underlayers /spl sim/5 /spl Aring/ thick provide improved growth and flatband voltage control of ALD HfO/sub 2/ films compared to thermal oxides. Optimized annealing conditions are shown to greatly reduce both fixed charge and interfacial oxide growth in the high-/spl kappa/ stacks. Extremely small flatband voltage shifts of

We report the fabrication and device characteristics of a 50 /spl Aring/ thick dual-layer gate dielectric with high interface quality (D/sub it/ and Q/sub f/ /spl sim/10/sup 10/ cm/sup 2/) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a /spl sim/40 /spl Aring/ thick oxynitride layer, through which slow O/sub 2/ diffusion is used to grow a /spl sim/10 /spl Aring/ thick SiO/sub 2/ at the interface. The small thickness of the SiO/sub 2/ layer reduces the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO/sub 2/ layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950/spl deg/C. >

This article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm