1. Asymmetric Keep-Out Zone of Through-Silicon Via Using 28-nm Technology Node
- Author
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Huang-Siang Lan, Y.-H. Huang, Jhih-Yang Yan, Michael Huang, Chee-Wee Liu, Sun-Rong Jan, Bigchoug Hung, Yi-Chung Huang, K.-T. Chan, and M.-T. Yang
- Subjects
Physics ,Field (physics) ,Through-silicon via ,Silicon ,business.industry ,media_common.quotation_subject ,Electrical engineering ,chemistry.chemical_element ,Absolute value ,Molecular physics ,Asymmetry ,Electronic, Optical and Magnetic Materials ,Stress field ,chemistry ,Node (physics) ,Electrical and Electronic Engineering ,business ,Radial stress ,media_common - Abstract
The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress ( $\vert \sigma _{r}\vert )$ does not equal to that of tangential stress ( $\vert \sigma _{\theta }\vert )$ on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.
- Published
- 2015
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