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This paper presents a logic inverter circuit consisting of both CMOS and GaN devices to drive high-torque DC motors requiring high voltages in various robotics applications. The GaN+CMOS inverter can be monolithically integrated with CMOS digital circuits on a single die, accommodating a 5V CMOS logic level input and providing a 30V output voltage using depletion-mode GaN HEMTs without negative gate bias circuitry. Electro-thermal simulations are also performed to analyze the temperature of CMOS devices affected by nearby GaN HEMTs.

We report on the growth of In0.30Ga0.70As channel high electron mobility transistor (HEMT) epi-layers on a 200-mm Si substrate by metal-organic-chemical-vapor-deposition. The HEMT layers were grown on the Si substrate by using a ~3- ${\mu }\text{m}$ thick epitaxial buffer composing of a Ge layer, a GaAs layer, and a compositionally graded and strain relaxed InAlAs layer. The optimized epitaxy has a threading dislocation density of less than $2 {\times } 10^{{7}}$ cm−2 and a root mean square surface roughness of ~6.7 nm. The device active layers include a ${ {\delta } }$ -doped InAlAs bottom barrier, a ~15-nm thick InGaAs channel, a ~8-nm InGaP top barrier layer and a heavily doped InGaAs contact layer. MOSHEMTs with channel length down to 130 nm were fabricated. The devices achieve a peak transconductance of ${\sim }450 ~{\mu }\text{S}/ {\mu }\text{m}$ at ${V} _{ D}$ of 0.5 V. The peak effective mobility ( ${\mu }_{\text {eff}}$ ) in a device with a channel length of 20 $ {\mu }\text{m}$ device channel was ~3700 cm2/ $\text{V} {\cdot }\text{s}$ .

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work.

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafers, two issues have to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and results in unbonded area. To address this, a CMP process that using conventional SiO 2 slurry with the addition of diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is that the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer onto a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate can be realized.

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafer, two issues need to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and create unbonded area. To address this, a CMP process that using conventional SiO 2 slurry with additional diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer to a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate is realized.

One effective approach to reduce the cost of GaN devices is to use 200 mm-diameter and 725 μm-thick p-Si substrates. We demonstrated RF and power GaN-on-Si HEMTs on small pieces of samples from 200 mm wafers using Au-contained process. f T /$f_{\max}$ of 36/33 GHz were achieved in 0.25 μm gate RF devices and breakdown voltage (BV off )>1200V was achieved in power devices. 200 mm wafers were fabricated using CMOS-compatible process and devices with BV off >850 V were achieved.

CBrCl 3 is shown to be a useful precursor for heavy p-type carbon doping of GaAs x P 1− x grown via metalorganic chemical vapor deposition (MOCVD) across a range of compositions. Structural and electrical properties of the GaAsP films were measured for various processing conditions. Use of CBrCl 3 decreased the growth rate of GaAsP by up to 32% and decreases x by up to 0.025. The dependence of these effects on precursor inputs is investigated, allowing C-doped GaAsP films to be grown with good thickness and compositional control. Hole concentrations of greater than 2×10 19 cm −3 were measured for values of x from 0.76 to 0.90.

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain.

GaN-on-Silicon growth by MOCVD is wildly discussed in the context of stress and strain management. The low bow AlGaN/GaN structure grew on 200mm Si(111) wafer was demonstrated in this study. After using the sapphire pits on the normal flat susceptor, the wafer bow and residual stress decrease to 21.27um and 0.28GPa tensile stress. The GaN quality and the Rs in HEMT also got huge improvement. The sub-micron devices also show the comparable results in DC and small signal characteristics.

We demonstrate the influence of the arsine partial pressure (p(AsH3)) on the quality of a GaAs layer grown on Ge substrate by metal organic chemical vapor deposition. The GaAs quality improves with p(AsH3) used during the 100 nm thick GaAs buffer layer. By growing a GaAs buffer layer at 630 °C with p(AsH3) of 5 mbar, we obtain a smooth GaAs layer with a root mean square roughness of 4.7 Å. This GaAs layer does not contain anti-phase boundaries. With these optimized growth parameters, we fabricate a virtual GaAs substrate on a 200 mm silicon wafer as a first step towards the integration of III–V devices on silicon., National Research Foundation of Singapore

The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (–OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of –OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of –OH groups from the ambient. This process results in defect-free bonded wafers. NRF (Natl Research Foundation, S’pore) Published version

This letter presents a fully integrated Class-J GaN monolithic microwave circuit power amplifier (PA), which is fabricated in Woolfspeed 0.25- $\mu \text{m}$ GaN-on-SiC technology. This PA is the first published design for the emerging IEEE 802.11ax application in the literature. When tested with 80-MHz 256-quadratic-amplitude modulation 802.11ax signal with 11.25-dB peak-to-average power ratio, the PA delivers average output power of 27.3–30.3 dBm from 4.9 to 5.9 GHz, with power-added efficiency of 16.7% to 27.3%, while meeting the standard specification of error vector magnitude below −32 dB.

An approach for heterogeneous integration of InGaAs MOSHEMTs and Si-CMOS is proposed and a high quality multi-layer transfer process is demonstrated in 200 mm wafer scale. Heterostructures for In0.30Ga0.70As MOSHEMTs were grown using MOCVD on 200 mm Si substrates with record low threading dislocation density of eff ) of ∼4900 cm2/Vs at sheet electron density (N) of 3 × 1012 cm−2 was achieved which is record among InxGa 1 -xAs (x T ) of ∼60 GHz was extracted for 150 nm channel length MOSHEMTs.

We present the first sub-10 nm diameter vertical nanowire transistors of any kind in any semiconductor system. These devices are InGaAs MOSFETs fabricated by a top-down approach using reactive ion etching, alcohol-based digital etch and Ni alloyed contacts. A record Ion of 350 μA/μm at Ioff = 100 nA/μm and Vdd = 0.5 V is obtained in a 7 nm diameter device. The same device exhibits a peak transconductance (gm, pk) of 1.7 mS/μm and minimal subthreshold swing (S) of 90 mV/dec at Vds = 0.5 V, achieving the highest quality factor (defined as the ratio gm, pk/S) of 19 reported in vertical nanowire transistors. Excellent scaling behavior is observed with gm, pk and Ion increasing as the diameter is shrunk down to 7 nm.

This work presents a GaN RF power amplifier with a common-source-common-gate (CS-CG) linearization technique, demonstrating device-circuit interactions using the physics-based MIT Virtual Source GaNFET (MVSG) model. A few device parameters are carefully chosen to investigate their effects on the circuit performance, as well as to suggest how to fabricate or choose a better GaN device for RF power amplifier design. The designed amplifier achieves 11dB gain at 6GHz, 51% drain efficiency at 35.3dBm Psat, and 39dBm output IP3 with 10V supply voltage. In this work, it is shown that the physical device parameters related to DC, RF, and thermal conditions affect the above circuit performance, especially linearity, and could be used to link the circuit performance to specific device level physics.

A method to integrate III-V compound semiconductors (GaN HEMT, InGaN LED, InGaAs HEMT or InGaP LED) with Si-CMOS on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily held on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. Through this method, a new generation of system with more functionality, better energy efficiency, and smaller form factor can be realized.

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems. Published version

Lineshape-fitting, using a model that takes into account of band tails, was performed on the photoluminescence spectra measured from InN samples at temperatures varying from 5 to 300 K. By analyzing how the fitted parameters varied with temperature, it was found that the previously observed blue and then red shift of emission peak position with increasing temperature is related to valence band tails. The initial blue-shift at low temperature is due to filling of valence band tails while the subsequent Varshni red-shift is due to lattice expansion. In a series of samples grown using increasing trimethylindium flow rates during metal organic chemical vapor deposition, the impurity potential that describes the width of the valence band tail increased from 18 to 26 meV, possibly due to more nitrogen vacancies being created in the material.

In this letter, a novel methodology to achieve output broadband matching is proposed. Based on this methodology, a broadband gallium nitride power amplifier (PA) with input matching and stabilization circuit integrated on-chip is designed. The implemented PA achieves a maximum drain efficiency of 62%-79.2% from 2.6 to 6.4 GHz (84.4% fractional bandwidth), with a saturated output power (Psat) of 34.3-35.8 dBm, while providing a gain larger than 10 dB. When tested with 802.11ac VHT80 MC9 (80 MHz, 256-QAM) with 11.3-dB peak-to-average power ratio, PA achieves a drain efficiency of 22.1%-25.2% with an average output power of 23-25.4 dBm across the whole band, while meeting the standard specification of error vector magnitude below -32 dB. NRF (Natl Research Foundation, S’pore) Accepted version

The integration of direct bandgap III-V semiconductors on Si substrate can enable efficient light emitters, and many applications that need light sources would be benefited, such as lighting, display, photonic integrated circuits (PICs), and on-chip optical communications. AlGaInP that is lattice-matched to GaAs is an efficient light emitting material which emits red to yellow-green light, depending on composition. It has been widely used for commercial red and yellow-green light emitting diodes (LEDs). To integrate AlGaInP on Si substrate, however, there are many challenges remaining, both in the epitaxy growth and integration processing. Here, we demonstrate our work on the epitaxy and wafer bonding of AlGaInP materials on 8″ Si substrates.

Here we present an initial demonstration of a dual junction step-cell using single junction (SJ) GaAs 0.76 P 0.24 cell, grown on Si 1−y Ge y /Si substrates, as the top cell and Si as the bottom cell. To demonstrate step-cell, two SJ cells are connected in series, without removing SiGe/Si carrier from III-V cell, and illuminated Si cell area is varied. Measured efficiency of optimized demo step-cell under 1 sun and without anti-reflective coating on III-V cell is ∼11.8% Using SJ cells characterization and optical data, we estimate maximum efficiency of bonded 1-μm GaAs 0.76 P 0.24 // 650-μm Si step-cell to be ∼26% at optimized total-to-top cell area ratio equal to 1.1. Results presented here show that step-cell can be used as added optimization design parameter for tandem cells.

High quality germanium (Ge), III–V (GaAs, GaN) on insulator substrates (“X”-OI, X = Ge, GaAs or GaN) are demonstrated on 200 mm Si wafer. The Ge or III–V epitaxial films are grown directly on the Si donor wafers using a metal-organic chemical vapour deposition (MOCVD). The epilayers are then bonded and transferred to another Si (001) handle wafers to form various “X”-OI substrates. The quality of the epitaxial films (in term of threading dislocations density, TDD) on the X-OI can be further improved through a thermal treatment to mid-106 /cm2.

In novel photovoltaic absorbers, it is often difficult to assess the root causes of low open-circuit voltages, which may be due to bulk recombination or sub-optimal contacts. In the present work, we discuss the role of temperature- and illumination-dependent device electrical measurements in quantifying and distinguishing these performance losses — in particular, for determining bounds on interface recombination velocities, band alignment, and minority carrier lifetime. We assess the accuracy of this approach by direct comparison to photoelectron spectroscopy. Then, we demonstrate how more computationally intensive model parameter fitting approaches can draw more insights from this broad measurement space. We apply this measurement and modeling approach to high-performance III-V and thin-film chalcogenide devices.

Two approaches for metalorganic chemical vapor deposition (MOCVD)-grown compositionally graded metamorphic buffers on 6° offcut bulk GaAs were investigated. The first approach consisted of tandem graded layers of InGaAs and InGaP with compositional grading of the In concentration. This tandem approach was found to be necessary because phase separation in the InGaAs alloys leads to surface roughening and high threading dislocation density when grading to lattice constants greater than that of In 0.30 Ga 0.70 As. An In x Ga 1− x As graded buffer was grown at 700 °C for low In concentration ( X In =0–0.10) and then the growth temperature was decreased to 450 °C for high In concentration ( X In =0.10–0.30) to suppress the phase separation. The growth temperature was then increased to 650 °C and the graded In y Ga 1− y P system was implemented to continue grading the lattice constant from In 0.30 Ga 0.70 As to InP, which allowed us to achieve InP on 6° offcut GaAs with a threading dislocation density of 7.9×10 6 cm −2 and an RMS surface roughness of 33.0 nm on a 40 μm×40 μm AFM scale. The second approach used GaAsSb alloys with compositional grading of the Sb concentration. Graded mixed-anion GaAsSb alloys grown at 575 °C did not exhibit phase separation, resulting in high quality InP lattice constant films on GaAs without the need to transition to another material system for compositional grading. We demonstrated a GaAsSb alloy on GaAs (with a grading rate of 1.06% strain/μm) lattice-matched to InP with a threading dislocation density of 4.7×10 6 cm −2 and a roughness of 7.4 nm on a 40 μm×40 μm AFM scale. It was further demonstrated that the threading dislocation density of the GaAsSb graded buffer can be lowered to 2.7×10 6 cm -2 with a slower grading rate (0.64% strain/μm).

Front end integration of III-V compound semiconductor devices with Si complimentary metal-oxide-semiconductor (CMOS) technology requires the development of commercially viable engineered substrates. The fabrication of engineered substrates currently utilizes technologies such as epitaxy, wafer bonding and layer exfoliation. In this paper we report on the development of GaAs-oninsulator (GaAsOI) structures without the use of Smart Cut technology. Epitaxial GaAs/Ge/GaAs stacks containing an embedded Ge sacrificial release layer were grown with metal-organic chemical vapor deposition (MOCVD) and exhibit both a low defect density as well as surface properties suitable for wafer bonding. A room temperature oxide-oxide bonding process was developed to enable the integration of substrates with a large difference in their coefficients of thermal expansion. The release of the donor substrate and transfer of the GaAs layer onto the handle substrate was realized through room temperature, gas-phase lateral etching of the embedded Ge sacrificial layer by exposure to xenon difluoride (XeF2). This GaAsOI fabrication process is shown to be successful on a small scale, though implementation for the production of commercially-viable large area GaAsOI substrates at full wafer scale is currently limited by the long gas transport distance associated with a wafer-scale lateral etching process. In order to explore possibilities for overcoming this limitation we established a model that identifies the rate limiting processes and discuss potential approaches that will allow for the implementation of our gas phase lateral etching process for the fabrication of large diameter GaAsOI substrates.

Heterojunction bipolar transistors (HBTs) with GaAs0.825P0.175 bases and collectors and In0.40Ga0.60P emitters were integrated monolithically onto Si substrates. The HBT structures were grown epitaxially on Si via metalorganic chemical vapor deposition, using SiGe compositionally graded buffers to accommodate the lattice mismatch while maintaining threading dislocation density at an acceptable level (∼3 × 106 cm−2). GaAs0.825P0.175 is used as an active material instead of GaAs because of its higher bandgap (increased breakdown voltage) and closer lattice constant to Si. Misfit dislocation density in the active device layers, measured by electron-beam-induced current, was reduced by making iterative changes to the epitaxial structure. This optimized process culminated in a GaAs0.825P0.175/In0.40Ga0.60P HBT grown on Si with a DC current gain of 156. By considering the various GaAsP/InGaP HBTs grown on Si substrates alongside several control devices grown on GaAs substrates, a wide range of threading disloca...

The authors present a comparison of metal organic chemical vapor deposition grown compositionally graded metamorphic buffers, which enable virtual substrates with very high quality crystal lattices with lattice constants from 5.45 to 5.65 A (threading dislocation density, ρt, around 104 cm−2). The structures, grown on GaP or GaAs, consist of graded In-fraction InGaP and AlInGaP or graded P-fraction GaAsP. They show that surface roughness and locally strained regions of phase separation (branch defects) limit misfit dislocation glide velocity and escalate threading dislocation density. High surface roughness and branch defects in (Al)InGaP lead to the lowest quality virtual substrates we observed, with ρt of around 3×106 cm−2. In contrast, graded mixed-anion films of GaAsP avoid branch defects and minimize surface roughness, giving superior defect densities, as low as 104 cm−2 at useful lattice constants halfway between that of Si and Ge. Tensile graded GaAs1−zPz layers yield the smoothest films (0.78 nm r...

We report on a direct epitaxial growth approach for the heterogeneous integration of high-speed III–V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBT) structures were successfully grown on Si-on-lattice-engineered- substrate (SOLES) and Ge-on-insulator-on-Si (GeOI/Si) substrates using molecular beam epitaxy. Structurally, the epiwafers exhibit sharp interfaces and a threading dislocation density of 3.5×10 7 cm −2 as measured by plan-view transmission electron microscopy. HBT devices fabricated on GeOI/Si substrates have current gain of 55–60 at a base sheet resistance of 650–700 Ω/sq, and f t and f max of around 220 GHz. HBT structures with DC and RF performance similar to those grown on lattice-matched InP were also achieved on patterned SOLES substrates with growth windows as small as 15×15 μm 2 . These results demonstrate a promising path of heterogeneous integration and selective placement of III–V devices at arbitrary locations on Si CMOS wafers.

The growth of InP nanowires by the VLS mechanism on Si 〈1 1 1〉 substrates with varying pre-growth treatments was investigated. When Au-catalyst particles were treated with trimethylindium before growth there was an increase in the fraction of catalyst particles yielding wire growth and in the number of these wires growing vertically from the substrate. This was confirmed using scanning electron microscopy, X-ray diffraction and energy dispersive X-ray spectroscopy. Cross-sectional transmission electron microscopy revealed that Au-catalyst particles exposed to PH3 before growth did not alloy with the underlying Si substrate. InP wires were also grown using Ag catalyst particles which do not alloy with the Si substrate. However, wire growth does not appear to be inhibited in this case. These results suggest that P is the primary cause for the both lack of growth from some catalyst particles and growth in directions other than the vertical 〈1 1 1〉 direction of the substrate.

We summarize our work on creating substrate platforms, processes, and devices for the monolithic integration of silicon CMOS circuits with III-V optical and electronic devices. Visible LEDs and InP HBTs have been integrated on silicon materials platforms that lend themselves to process integration within silicon fabrication facilities. We also summarize research on tensile Ge, which could be a high mobility material for III-V MOS, and research on an in-situ MOCVD Al2O3/GaAs process for III-V MOS.

The integration of light emitting devices on silicon substrates ha s attracted intensive research for many years. In contrast to the InGaN light emitting diodes (LEDs) whose epitaxy technology on Si substrates is robust and mature, the epitaxy of other compound semiconductor light emitting materials covering the visible wavelength range on Si is still challenging. We have studied epitaxial growth of red InGaP light emitting materials on engineered Ge-on-Si substrates. Ge-on-Si was grown on 8’’ Si substrates in a metal organic chemical vapour deposition (MOCVD) reactor using two-step growth and cycling annealing. Threading dislocation densities (TDDs) were controlled to as low as 10 6 /cm 2 by using As-doped Ge initiation. A GaAs buffer layer and lattice-matched InGaP LEDs were grown on the Ge-on-Si sequentially in the same MOCVD process and red LEDs are demonstrated. InGaP multiple-quantum-well LED structures were grown on full 8’’ Ge -on-Si substrates and characterized. Keywords: InGaP LEDs, Ge-on-Si substrate, MOCVD epitaxy

We have achieved the first monolithically integrated triple-junction InGaP/GaAsP/SiGe solar cell on Si substrate, achieving an adjusted efficiency of 20% AM0 1-sun. The practical achievable maximum AM0 efficiency for the optimal cell near this lattice constant is 39%. The combination of this high efficiency with the ability to process such cells on larger area lower-cost silicon substrates motivates our continued advancement of this technology. Radiation testing of 4Power cells, up to 2.7 × 1012 p+/cm2 (10MeV) show excellent radiation hardness; the novel SiGe bottom junction shows no measurable degradation after proton radiation testing, verifying such cells have application in air and space photovoltaics. Furthermore, because of the combination of high efficiency and low mass density, 4Power InGaP/GaAsP/SiGe solar cells can reach AM0 specific power approaching 1400 W/kg, greatly exceeding that of current state of the art InGaP/(In)GaAs/Ge space cells that are ∼500 W/kg. The high efficiency afforded by the unique tailoring of the multijunction bandgap cell can provide a realistic maximum of ∼500 W/m2 at AM0 1-sun.

The growth and formation of Ge nanocrystals embedded into a silicon oxide (SiO2) system synthesized by furnace annealing have been studied based on the Ge content of co-sputtered Ge–SiO2 films. The influence of a silicon oxide diffusion barrier inserted between the co-sputtered film and the substrate on the formation of the Ge nanocrystals is also examined. We found that the effect of Si reduction on the Ge oxides plays an important role in the synthesis of Ge nanocrystals in co-sputtered Ge plus SiO2 samples with high Ge oxide concentration (80%) relative to the elemental Ge concentration (20%). The oxide diffusion barrier influenced the distribution of the nanocrystals by preventing Ge from diffusing into the substrate such that nanocrystals were formed throughout the film. When the Ge concentration was much higher (75%) than the Ge oxide concentration, the contribution from the effect of Si reduction on the Ge oxides in the formation of the nanocrystals is not significant. Again, the oxide diffusion barrier was very effective in preventing Ge atoms from diffusing into the Si substrate, and significant coarsening of the nanoclusters was observed in these samples.

A dual channel heterostructure consisting of strained-Si/strained-Si1−yGey on relaxed Si1−xGex (y > x), provides a platform for fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs) with high hole mobilities (μeff) which depend directly on Ge concentration and strain in the strained-Si1−yGey layer. Ge out-diffuses from the strained-Si1−yGey layer into relaxed Si1−xGex during high temperature processing, reducing peak Ge concentration and strain in the strained-Si1−yGey layer and degrades hole μeff in these dual channel heterostructures. A heterostructure consisting of strained-Si/strained-Si1−yGey/strained-Si, referred to as a trilayer heterostructure, grown on relaxed Si1−xGex has much reduced Ge out-flux from the strained-Si1−yGey layer and retains higher μeff after thermal processing. Improved hole μeff over similar dual channel heterostructures is also observed in this heterostructure. This could be a result of preventing the hole wavefunction tunneling into the low μeff relaxed Si1−xGex layer due to the additional valence band offset provided by the underlying strained-Si layer. A diffusion coefficient has been formulated and implemented in a finite difference scheme for predicting the thermal budget of the strained SiGe heterostructures. It shows that the trilayer heterostructures have superior thermal budgets at higher Ge concentrations. Ring-shaped MOSFETs were fabricated on both platforms and subjected to various processing temperatures in order to compare the extent of μeff reduction with thermal budget. Hole μeff enhancements are retained to a much higher extent in a trilayer heterostructure after high temperature processing as compared to a dual channel heterostructure. The improved thermal stability and hole μeff of a trilayer heterostructure makes it an ideal platform for fabricating high μeff MOSFETs that can be processed over higher temperatures without significant losses in hole μeff.

High-performance p/sup +//n GaAs solar cells were grown and processed on compositionally graded Ge-Si/sub 1-x/Ge/sub x/-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm/sup 2/ solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm/sup 2/ did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.

The reaction of Ni with Ge, Si 0.75 Ge 0.25 and Si using rapid thermal annealing (RTA) and in-situ annealing method at 400°C produces different phases, as revealed by cross-sectional transmission electron microscopy (TEM). A uniform film of nickel germanide (NiGe) was formed at 400°C for the Ni reaction with Ge using the in-situ annealing technique, whereas Ni 3 Ge 2 and NiGe phases were found using the RTA method. For the reaction between Ni and Si, a highly textured NiSi film was obtained at 400°C for RTA whereas Ni 3 Si 2 and NiSi were found using the in-situ annealing method. On the other hand, a relatively uniform NiSiGe was formed using RTA; Ni 3 (Si 1-y Ge y ) 2 and Ni(Si 1-x Ge x ) (x

The diffusion behavior of ion-implanted arsenic in strained Si/relaxed Si 0.8 Ge 0.2 structures is studied during rapid thermal processing in oxygen (interstitial injection) and ammonia (vacancy injection). During rapid thermal processing in an oxygen ambient, arsenic diffusion in SiGe is reduced, while an ammonia ambient produces strong enhancement, especially for short times. The results suggest that arsenic diffusion in SiGe has a stronger vacancy component than arsenic diffusion in Si. Vacancy injection is also observed to enhance the diffusivity of Ge from relaxed SiGe into strained Si.

In order to study the luminescent efficiency of InGaAs quantum wells on Si via SiGe interlayers, identical In0.2Ga0.8As quantum well structures with GaAs and Al0.25Ga0.75As cladding layers were grown on several substrates by an atmospheric metalorganic vapor deposition system. The substrates used include GaAs, Si, Ge, and SiGe virtual substrates. The SiGe virtual substrates were graded from Si substrates to 100% Ge content. Because of the small lattice mismatch between GaAs and Ge (0.07%), high-quality GaAs-based thin films with threading dislocation densities

We have determined the critical cracking thickness, or the thickness beyond which crack formation is favored, in GaAs films grown on Si and SiGe virtual substrates analytically and experimentally. The analytical model predicts a critical cracking thickness proportional to the biaxial modulus and the crack resistance of the GaAs film, and inversely proportional to the square of the thermal stress and a nondimensional crack resistance number Z. This Z number is determined by the mechanical properties of the GaAs film for a system without substrate damage, and is also determined by the mechanical properties of the substrate for a system with substrate damage. The experimentally determined critical thicknesses were in general greater than the analytically derived values due to the kinetic barriers to crack nucleation, which were not taken into consideration in the models. In addition, we have observed an asymmetric crack array formation, where arrays running in the 〈110〉 substrate off-cut direction are favored. We have also performed finite element modeling of the crack systems to study the evolution of thermal stress around crack planes in the GaAs film.

GaAs/AlxGa(1−x)As quantum well lasers have been demonstrated via organometallic chemical vapor deposition on relaxed graded Ge/GexSi(1−x) virtual substrates on Si. A number of GaAs/Ge/Si integration issues including Ge autodoping behavior in GaAs, reduced critical thickness due to thermal expansion mismatch, and complications with mirror facet cleaving have been overcome. Despite unoptimized laser structures with high series resistance and large threshold current densities, surface threading dislocation densities for GaAs/AlGaAs lasers on Si substrates as low as 2×106 cm−2 permitted continuous room-temperature lasing at a wavelength of 858 nm. The laser structures are uncoated edge-emitting broad-area devices with differential quantum efficiencies of 0.24 and threshold current densities of 577 A/cm2. Identical devices grown on commercial GaAs substrates showed similar behavior. This comparative data agrees with previous measurements of near-bulk minority carrier lifetimes in GaAs grown on Ge/GeSi/Si substrates.

Here, we use a bottom-up approach to estimate the manufacturing costs of GaAsP/Si dual junction (DJ) solar cells, fabricated using step-cell technology. Step-cell features facilitate fast epitaxial lift-off while at the same time can be used to optimize tandem cell performance. The estimated step-cell costs are compared with commercially available GaInP/GaAs/Ge triple junction solar cells. For III-V layers grown on Si, it is assumed that graded Si1-yGey buffer layers are used to manage III-V and Si lattice mismatch. Three different scenarios are considered, basing future estimates on an extensive literature survey. The results show distinct cost benefits of Si based growth versus Ge, mainly due to substrate recycling enabled by epitaxial lift-off of III-V layers. Furthermore, the results indicate that major cost contributors for bonded GaAsP/Si step-cells are metal-organic chemical vapor deposition growth of III-V layers and wafer carrier and bonding, with ∼$9.1/W manufacturing costs for a 30% efficient c...

Single junction InGaP/GaAs solar cells displaying high efficiency and record high open circuit voltage values have been grown by metalorganic chemical vapor deposition on Ge/graded SiGe/Si substrates. Open circuit voltages as high as 980 mV under AM0 conditions have been verified to result from a single GaAs junction, with no evidence of Ge-related sub-cell photoresponse. Current AM0 efficiencies of close to 16% have been measured for a large number of small area cells, whose performance is limited by non-fundamental current losses due to significant surface reflection resulting from greater than 10% front surface metal coverage and wafer handling during the growth sequence for these prototype cells. It is shown that at the material quality currently achieved for GaAs grown on Ge/SiGe/Si substrates, namely a 10 nanosecond minority carrier lifetime that results from complete elimination of anti-phase domains and maintaining a threading dislocation density of approximately 8 x 10(exp 5) per square centimeter, 19-20% AM0 single junction GaAs cells are imminent. Experiments show that the high performance is not degraded for larger area cells, with identical open circuit voltages and higher short circuit current (due to reduced front metal coverage) values being demonstrated, indicating that large area scaling is possible in the near term. Comparison to a simple model indicates that the voltage output of these GaAs on Si cells follows ideal behavior expected for lattice mismatched devices, demonstrating that unaccounted for defects and issues that have plagued other methods to epitaxially integrate III-V cells with Si are resolved using SiGe buffers and proper GaAs nucleation methods. These early results already show the enormous and realistic potential of the virtual SiGe substrate approach for generating high efficiency, lightweight and strong III-V solar cells.

Oxidation of strained-Si/relaxed-SiGe heterostructure grown by UHVCVD method using a rapid thermal processing technique in N2O ambient is investigated. The electrical properties of the grown oxide have been characterized using a MOS structure. Hole confinement in the SiGe layer at low field is observed from the capacitance–voltage curve and this suggests that the strain in the initially strained Si epilayer is retained after oxidation. The experimental results are compared with simulation results obtained from a 1D Poisson solver. Dit and Qf/q values are estimated to be 3×1011 cm−2 eV−1 and −1.2×1011 cm−2, respectively. These high values of Dit and negative Qf/q could possibly be due to Ge out diffusion and pile up at the SiO2/strained-Si interface. The oxide exhibits an excellent breakdown field of 15 MV cm−1.

Epitaxial transparent-substrate light-emitting diodes (ETS-LEDs) have been fabricated on optimized graded buffers of InxGa1−xP on GaP (∇x[InxGa1−x]P/GaP) that feature controlled threading dislocation densities of 3×106 cm−2. The ETSLEDs show increasing efficiency from 575 nm to 655 nm, in marked contrast to previous reports where performance drops above 600 nm, and feature the lowest spectral widths ever reported in ∇x[InxGa1−x]P/GaP. The improvement over earlier reports is attributed to large mean dislocation spacings in optimized ∇x[InxGa1−x]P/GaP, which are an order of magnitude greater than the mean carrier diffusion length. A slight performance decline remains at 655 nm, but the overall performance of this first generation of ETS-LEDs is promising.

Dual junction GaInP/GaAs solar cells have been grown and fabricated on Si substrates using relaxed, compositionally graded SiGe buffer layers that provide a nearly lattice-matched low threading dislocation Ge surface for subsequent cell growth. The dual junction cells on SiGe/Si displayed high open circuit voltages in excess of 2.2 V, compared to 2.34 V for control cells on GaAs, that are consistent with maintaining the 1.8/spl times/10/sup 6/ cm/sup -2/ threading dislocation density throughout the cell structure. Even with total current output limited by large grid coverage and high reflectance, total area AM1.5G efficiency is 16.8%, with active area efficiency at 18.6%. The high V/sub oc/ establishes that SiGe metamorphic buffers are viable for integrating III-V multijunction cells on Si in a monolithic process.

The minority carrier lifetime of electrons (τn) in p-type GaAs double heterostructures grown on GaAs substrates and compositionally graded Ge/Si1−xGex/Si (SiGe) substrates with varying threading dislocation densities (TDDs) were measured at room temperature using time-resolved photoluminescence. The electron lifetimes for homoepitaxial GaAs and GaAs grown on SiGe (TDD∼1×106 cm−2) with a dopant concentration of 2×1017 cm−3 were ∼21 and ∼1.5 ns, respectively. The electron lifetime measured on SiGe was substantially lower than the previously measured minority carrier hole lifetime (τp) of ∼10 ns, for n-type GaAs grown on SiGe substrates with a similar residual TDD and dopant concentration. The reduced lifetime for electrons is a consequence of their higher mobility, which yields an increased sensitivity to the presence of dislocations in GaAs grown on metamorphic buffers. The disparity in dislocation sensitivity for electron and hole recombination has significant implications for metamorphic III-V devices.

Ultra-high vacuum scanning tunneling microscopy and depth profiling X-ray photoelectron spectroscopy were used to evaluate two methods for cleaning Si 1− x Ge x (001) films using ex-situ surface oxidation followed by in-situ oxide desorption at temperatures ≤ 1025°C. Dry ultra-violet ozone cleaning was found to be fast, simple, and highly effective for cleaning Si 1− x Ge x (001) surfaces with a wide range of Ge content as well as standard Si(001) surfaces, consistently yielding lower surface particulate densities than a standard wet chemical cleaning technique.

Here we present detailed balance efficiency limit for a novel two-terminal dual and triple junction “step-cell” under AM 1.5G and AM 0 incident spectrums. The step-cell is a multi-junction (MJ) solar cell in which part of the top cell is removed, exposing some of the bottom cell area to unfiltered incident light, thus increasing bottom cell's photogenerated current. Optical generation of the bottom cell is modeled in two parts: step part, limited by the bottom cell bandgap, and conventional part, additionally limited by the top cell absorption. Our results show that conventionally designed MJ cell with optimized bandgap combination of 1.64 eV/0.96 eV for dual junction and 1.91 eV/1.37 eV/0.93 eV for triple junction has the highest theoretical efficiency limit. However, the step-cell design provides significant efficiency improvement for cells with non-optimum bandgap values. For example, for 1.41 eV ( ∼GaAs)/Si dual junction under AM 1.5G, efficiency limit increases from ∼21% in a conventional design to 38.7% for optimized step-cell. Similar benefits are observed for three-junction step-cell and for AM 0 spectrum studied here. Step-cell relaxes bandgap requirements for efficient MJ solar cells, providing an opportunity for a wider selection of materials and cost reduction.

The effect of germanium concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal–insulator–semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO2 cosputtered middle layer (i.e., lower Ge concentration), even though a higher charge storage capability was obtained from devices with a thinner RTO layer, the charge retention capability was poorer as compared to devices with a thicker RTO layer.

Direct integration of GaP/Si must face a small, but non-negligible lattice constant mismatch, which due to thermal expansion differences between GaP and Si, reaches 0.5% at 900 K. This lattice mismatch results in the nucleation of misfit dislocations at the GaP/Si interface, requiring careful strain management and refinement of epitaxial processes. However, Si 0.88 Ge 0.12 virtual substrates grown on Si provide a nearly ideal lattice-matched template for GaP epitaxy. This paper describes the successful heteroepitaxial integration of lattice-matched GaP/Si 0.88 Ge 0.12 /Si, based upon the previously-demonstrated methodology for successful GaP/Si integration, which provides a potential alternative pathway for low defect density III–V/Si multijunction photovoltaics, parallel to that of direct GaP/Si.