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Methods to integrate different crystal orientations, strain states, and compositions of semiconductors in planar and preferably flexible configurations may enable nontraditional sensing-, stimulating-, or communication-device applications. We combine crystalline-silicon nanomembranes, patterning, membrane transfer, and epitaxial growth to demonstrate planar arrays of different orientations and strain states of Si in a single membrane, which is then readily transferable to other substrates, including flexible supports. As examples, regions of Si(001) and Si(110) or strained Si(110) are combined to form a multicomponent, single substrate with high-quality narrow interfaces. We perform extensive structural characterization of all interfaces and measure charge-carrier mobilities in different regions of a 2D quilt. The method is readily extendable to include varying compositions or different classes of materials.

In order to increase the failure temperature of Ta diffusion barrier for Cu, we investigated the effect of a thin V insertion layer (100 A) into Ta film with/without ion bombardment on Ta diffusion barrier performance in Cu metallization. When the Ta/V/Ta diffusion barrier was deposited without concurrent ion bombardment, the insertion of the thin V layer into Ta film was not effective to improve the barrier performance of Ta film, because of the thermal instability of the Ta/V/Ta multilayer caused by the reaction between the Ta/V/Ta films and Si substrate. Meanwhile, when the Ta/V/Ta diffusion barrier was deposited with ion bombardment, the insertion of the thin V layer into Ta film improved barrier properties significantly. This was attributed not only to the densification of grain boundaries in Ta/V/Ta films, but also to the formation of two thermally stable sharp interfaces between Ta and V by ion bombardment, resulting in the reduction of the fast diffusion of Cu through Ta/V/Ta films.

We report thermoelectric measurements on a silicon nanoribbon in which an integrated gate provides strong carrier confinement and enables tunability of the carrier density over a wide range. We find a significantly enhanced thermoelectric power factor that can be understood by considering its behavior as a function of carrier density. We identify the underlying mechanisms for the power factor in the nanoribbon, which include quantum confinement, low scattering due to the absence of dopants, and, at low temperatures, a significant phonon-drag contribution. The measurements set a target for what may be achievable in ultrathin nanowires.

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.