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Wearable electronics need miniaturized, safe, and flexible power sources. Lithium-ion battery is a strong candidate as high performance flexible battery. The development of flexible materials for battery electrodes suffers from the limited material choices. In this paper, we present integration strategy to rationally design materials and processes to report flexible inorganic lithium-ion microbattery with no restrictions on the materials used. The battery shows an enhanced normalized capacity of 147 μAh/cm2 when bent.

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin $(25~\mu{\rm m})$ silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage $({\rm V}_{\rm ramp})$ breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer.

The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex's folded pattern for ultra-compact design.

In today's traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry's most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications.

We report the inherent increase in capacitance per unit planar area of state-of-the art high-κ integrated metal/insulator/metal capacitors (MIMCAPs) fabricated on flexible silicon fabric with release-first process. We methodically study and show that our approach to transform bulk silicon (100) into a flexible fabric adds an inherent advantage of enabling higher integration density dynamic random access memory (DRAM) on the same chip area. Our approach is to release an ultra-thin silicon (100) fabric (25 µm thick) from the bulk silicon wafer, then build MIMCAPs using sputtered aluminium electrodes and successive atomic layer depositions (ALD) without break-ing the vacuum of a high-κ aluminium oxide sandwiched between two tantalum nitride layers. This result shows that we can obtain flexible electronics on silicon without sacrificing the high density integration aspects and also utilize the non-planar geometry associated with fabrication process to obtain a higher integration density compared to bulk silicon integration due to an increased normalized capacitance per unit planar area. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Implementation of memory on bendable substrates is an important step toward a complete and fully developed notion of mechanically flexible computational systems. In this paper, we have demonstrated a simple fabrication flow to build metal-insulator-metal capacitors, key components of dynamic random access memory, on a mechanically flexible silicon (100) fabric. We rely on standard microfabrication processes to release a thin sheet of bendable silicon (area: 18 cm2 and thickness: 25 μm) in an inexpensive and reliable way. On such platform, we fabricated and characterized the devices showing mechanical robustness (minimum bending radius of 10 mm at an applied strain of 83.33% and nominal strain of 0.125%) and consistent electrical behavior regardless of the applied mechanical stress. Furthermore, and for the first time, we performed a reliability study suggesting no significant difference in performance and showing an improvement in lifetime projections.

We report short circuit current (Jsc) enhancement in crystalline silicon (C-Si) photovoltaic (PV) using low-cost Ohmic contact engineering by integration of Nickel mono-silicide (NiSi) for back contact metallization as an alternative to the status quo of using expensive screen printed silver (Ag). We show 2.6 mA/cm2 enhancement in the short circuit current (J sc ) and 1.2 % increment in the efficiency by improving the current collection due to the low specific contact resistance of the NiSi on the heavily Boron (B) doped Silicon (Si) interface.

Future wearable electronics require not only flexibility but also preservation of the perks associated with today's high-performance, traditional silicon electronics. In this work we demonstrate a state-of-the-art fin-shaped field-effect transistor (FinFET)-based, out-of-plane strain sensor on flexible silicon through transforming the bulk device in a transfer-less process. The device preserves the functionality and high performance associated with its bulk, inflexible state. Furthermore, gate leakage current shows sufficient dependence on the value of the applied out-of-plane strain that enables permits use of the flexible device as a switching device as well as a strain sensor.

Commercialization of wearable electronics requires miniaturized, flexible power sources. Lithium ion battery is a strong candidate as the next generation high performance flexible battery. The development of flexible materials for battery electrodes suffers from the limited material choices. In this work, we present a flexible inorganic lithium-ion battery with no restrictions on the materials used. The battery showed an enhanced normalized capacity of 146 µAh/cm2.

We report out-of-plane strain effect on silicon based flexible FinFET, with sub 20 nm wide fins and hafnium silicate based high-κ gate dielectric. Since ultra-thin inorganic solid state substrates become flexible with reduced thickness, flexing induced strain does not enhance performance. However, detrimental effects arise as the devices are subject to various out-of-plane stresses (compressive and tensile) along the channel length.

In today's digital age, the increasing dependence on information also makes us vulnerable to potential invasion of privacy and cyber security. Consider a scenario in which a hard drive is stolen, lost, or misplaced, which contains secured and valuable information. In such a case, it is important to have the ability to remotely destroy the sensitive part of the device (e.g., memory or processor) if it is not possible to regain it. Many emerging materials and even some traditional materials like silicon, aluminum, zinc oxide, tungsten, and magnesium, which are often used for logic processor and memory, show promise to be gradually dissolved upon exposure of various liquid medium. However, often these wet processes are too slow, fully destructive, and require assistance from the liquid materials and their suitable availability at the time of need. This study shows Joule heating effect induced thermal expansion and stress gradient between thermally expandable advanced polymeric material and flexible bulk monocrystalline silicon (100) to destroy high-performance solid state electronics as needed and under 10 s. This study also shows different stimuli-assisted smartphone-operated remote destructions of such complementary metal oxide semiconductor electronics.

A highly manufacturable deep reactive ion etching based process involving a hybrid soft/hard mask process technology shows high aspect ratio complex geometry Lego-like silicon electronics formation enabling free-form (physically flexible, stretchable, and reconfigurable) electronic systems.

Today's mainstream flexible electronics research is geared towards replacing silicon either totally, by having organic devices on organic substrates, or partially, by transferring inorganic devices onto organic substrates. In this work, we present a pragmatic approach combining the desired flexibility of organic substrates and the ultra-high integration density, inherent in silicon semiconductor industry, to transform bulk/inflexible silicon into an ultra-thin mono-crystalline fabric. We also show the effectiveness of this approach in achieving fully flexible electronic systems. Furthermore, we provide a progress report on fabricating various memory devices on flexible silicon fabric and insights for completely flexible memory modules on silicon fabric.

Neuromorphic computer will need folded architectural form factor to match brain cortex's folded pattern for ultra-compact design. In this work, we show a state-of-the-art CMOS compatible pragmatic fabrication approach of building structurally foldable and densely integrated neuromorphic devices for non-volatile memory applications. We report the first ever memristive devices with the size of a motor neuron on bulk mono-crystalline silicon (100) and then with trench-protect-release-recycle process transform the silicon wafer with devices into a flexible and semi-transparent silicon fabric while recycling the remaining wafer for further use. This process unconditionally offers the ultra-large-scale-integration opportunity - increasingly critical for ultra-compact memory.

With the emergence of cloud computation, we are facing the rising waves of big data. It is our time to leverage such opportunity by increasing data usage both by man and machine. We need ultra-mobile computation with high data processing speed, ultra-large memory, energy efficiency and multi-functionality. Additionally, we have to deploy energy-efficient multi-functional 3D ICs for robust cyber-physical system establishment. To achieve such lofty goals we have to mimic human brain, which is inarguably the world’s most powerful and energy efficient computer. Brain’s cortex has folded architecture to increase surface area in an ultra-compact space to contain its neuron and synapses. Therefore, it is imperative to overcome two integration challenges: (i) finding out a low-cost 3D IC fabrication process and (ii) foldable substrates creation with ultra-large-scale-integration of high performance energy efficient electronics. Hence, we show a low-cost generic batch process based on trench-protect-peel-recycle to fabricate rigid and flexible 3D ICs as well as high performance flexible electronics. As of today we have made every single component to make a fully flexible computer including non-planar state-of-the-art FinFETs. Additionally we have demonstrated various solid-state memory, movable MEMS devices, energy harvesting and storage components. To show the versatility of our process, we have extended our process towards other inorganic semiconductor substrates such as silicon germanium and III-V materials. Finally, we report first ever fully flexible programmable silicon based microprocessor towards foldable brain computation and wirelessly programmable stretchable and flexible thermal patch for pain management for smart bionics.

We demonstrate a buried contact based novel test structure for direct contact resistivity measurement of graphene-metal interfaces. We also observe excellent contact resistivity ~1 μO-cm2 without any additional surface modification suggesting that the intrinsic Au-graphene contact is sufficient for achieving devices with low contact resistance. The chemical mechanical polishing less test structure and data described herein highlights an ideal methodology for systematic screening and engineering of graphene-metal contact resistivity to enable low power high speed carbon electronics.

In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.

Flexible memory can enable industrial, automobile, space, and smart grid centered harsh/extreme environment focused electronics application(s) for enhanced operation, safety, and monitoring where bent or complex shaped infrastructures are common and state-of-the-art rigid electronics cannot be deployed. Therefore, we report on the physical-mechanical-electrical characteristics of a flexible ferroelectric memory based on lead zirconium titanate as a key memory material and flexible version of bulk mono-crystalline silicon (100). The experimented devices show a bending radius down to 1.25 cm corresponding to 0.16% nominal strain (high pressure of ∼260 MPa), and full functionality up to 225 °C high temperature in ambient gas composition (21% oxygen and 55% relative humidity). The devices showed unaltered data retention and fatigue properties under harsh conditions, still the reduced memory window (20% difference between switching and non-switching currents at 225 °C) requires sensitive sense circuitry for proper functionality and is the limiting factor preventing operation at higher temperatures.

A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)-(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational voltages to achieve coercive electric fields, reduces the sol-gel coating cycles required (i.e., more cost-effective), and, fabrication wise, is more suitable for further scaling of lateral dimensions to the nano-scale due to the larger feature size-to-depth aspect ratio (critical for ultra-high density non-volatile memory applications). Utilizing the inverse proportionality between substrate's thickness and its flexibility, traditional PZT based FeRAM on silicon is transformed through a transfer-less manufacturable process into a flexible form that matches organic electronics' flexibility while preserving the superior performance of silicon CMOS electronics. Each memory cell in a FeRAM array consists of two main elements; a select/access transistor, and a storage ferroelectric capacitor. Flexible transistors on silicon have already been reported. In this work, we focus on the storage ferroelectric capacitors, and report, for the first time, its performance after transformation into a flexible version, and assess its key memory parameters while bent at 0.5 cm minimum bending radius.

Neutrophil candidacidal function was measured by a chromium-51 (51Cr) release technique, using Candida guilliermondii as the test organism. The effect of varying the neutrophil:candida ratio, the time course of 51Cr release, the effect of different serum concentrations, and the reproducibility of the technique were investigated. Results from 33 experiments, using neutrophils from 35 normal donors and six patients with known neutrophil defects, show the technique to be a reliable and reproducible assay of candida killing. The chromium release assay has the advantage of being easy to perform and not liable to subjective errors.