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In this paper, in order to suppress unwanted current paths originating from adjacent cells in a passive crossbar array based on resistive random access memory (RRAM) without extrinsic switching devices, 1-diode type RRAM which consists of a 0.2% chromium-doped strontium titanate (Cr-) film deposited on a silicon substrate, was proposed for high packing density, and intrinsic rectifying characteristics from the current versus voltage characteristics were successfully demonstrated.

We report the effect of hydrogen annealing on the gate-leakage-current and switching characteristics of metal-alumina-nitride-oxide-silicon (MANOS) capacitors by analyzing their negative-/positive-bias instability (NBI/PBI). One sample, namely, A, is annealed with rapid thermal annealing (RTA), and the other sample, namely, B, is first annealed with RTA and then further annealed in a furnace, using a N2-H2 (98% nitrogen and 2% hydrogen) gas mixture. In the NBI/PBI experiments, the flatband voltage shift ΔVFB is observed to be smaller, i.e., the gate-leakage-current density is reduced for sample B at gate voltages less than ±3 V, a domain where trap-assisted tunneling is dominant. However, ΔVFB increases rapidly for the same sample at gate voltages larger than ±6 V, a domain where the modified Fowler-Nordheim tunneling (MFNT) is dominant, which indicates faster program-and-erase characteristics. These results show that additional hydrogen annealing can improve both device reliability and switching characteristics of the MANOS-type memory by reducing interface traps between the silicon substrate and silicon oxide layers, as well as turn-on voltages for MFNT.

The paper presents the passivation effect of post-annealing gases on the negative bias temperature instability of metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon (MONOS) capacitors. MONOS samples annealed at 850 °C for 30 s by a rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing gases N 2 and N 2 –H 2 (2% hydrogen and 98% nitrogen gas mixture) at 450 °C for 30 min. MONOS samples annealed in an N 2 –H 2 environment are found to have lowest oxide trap charge density shift, Δ N ot = 8.56 × 10 11 cm −2 , and the lowest interface-trap density increase, Δ N it = 4.49 × 10 11 cm −2 among the three samples as-deposited, annealed in N 2 and N 2 –H 2 environments. It has also been confirmed that the same MONOS samples have the lowest interface-trap density, D it = 0.834 × 10 11 eV −1 cm −2 , using small pulse deep level transient spectroscopy. These results indicate that the density of interface traps between the silicon substrate and the tunneling oxide layer are significantly reduced by the additional furnace annealing in the N 2 –H 2 environment after the RTA.

ZnO-based charge-trap Flash technology using a resistive switching mechanism is demonstrated for next-generation nonvolatile memory. This device consists of metal/ZnO/nitride/oxide/silicon in order to make use of the electrical transport in the ZnO resistive switching layer. Compared to the previous devices with perovskite oxide materials used as a conduction path, the proposed device shows faster switching speeds (10 ns/100 μs), lower operation voltages ( ±7 V) for the program/erase ( P/E) states, and higher endurance (106 P/E cycles), along with comparable retention properties.

The authors report a silicon-based one-diode–type resistive-switching memory (RRAM) device with self-rectifying properties and high electrical properties. The RRAM cell consisted of Al/Cr–SrTiO3/Si and revealed intrinsic diode properties, so that unwanted sneaky currents could be removed from an RRAM crossbar array without extra switching devices. The insulator–metal transition property of the proposed device was explained using the space-charge–limited conduction mechanism. The memory device showed good characteristics including high ON/OFF ratio (~106), low reset current (~10-11 A), high speed at low voltage (200 ns, 2 V), and reasonable endurance (>104 cycles) and retention characteristics (>104 s).

In this paper, we propose a charge-trap flash memory device using a ferroelectric material, Sr0.7Bi2.3Nb2O9 (SBN), with spontaneous polarization as a blocking layer. This device consists of metal/SBN/nitride/oxide/silicon and has an advantage in the carrier injection into the nitride from the silicon due to polarization charges formed in the ferroelectric material. Compared to conventional metal/oxide/nitride/oxide/silicon memory devices, the proposed devices showed a larger memory window (7 V), faster program/erase (P/E) speeds (100/500 μs), and higher endurance (105 P/E cycles) with comparable retention properties.

We examined the origin of the charge traps in bothSiO2/Si3N4/SiO2 (ONO) and Al2O3/Si3N4/SiO2 (ANO) structures and their effect on the memory characteristics by capacitance-voltage (C-V) measurements and deep level transient spectroscopy (DLTS). A larger memory window was observed by C-V for ANO, due to its higher trap density. The DLTS showed that nitride traps are dominant in ANO, while more Si/SiO2 interface-related traps are observed in ONO. The ANO capacitor outperforms the ONO one in terms of both the program efficiency and retention, which is attributed to the reduced number of interface traps in ANO.