1. Cost and power/performance optimized 20nm SoC technology for advanced mobile devices
- Author
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Benjamin John Bowers, Y.J. Mii, C.C. Wu, J. Fischer, Lixin Ge, Chock H. Gan, M. Cao, Xiangdong Chen, Ying Chen, Foua Vang, K.L. Cheng, P. Chidambaram, Da Yang, Sei Seung Yoon, Geoffrey Yeap, Joseph Wang, Ohsang Kwon, J. Cheng, Esin Terzioglu, John Jianhong Zhu, Robert J. Bucki, Giridhar Nallapati, Ming Cai, and J.Y. Sheu
- Subjects
Cost reduction ,Interconnection ,Engineering ,business.industry ,Hardware_INTEGRATEDCIRCUITS ,Multiple patterning ,Electronic engineering ,Mobile broadband modem ,Node (circuits) ,Context (language use) ,Routing (electronic design automation) ,Chip ,business - Abstract
A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.
- Published
- 2014
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