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An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-chip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 /spl times/5 mm/sup 2/ chip containing all the above features is fabricated by 0.18-/spl mu/m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.

Increasing complexity of a system-on-chip design demands efficient on-chip interconnection architecture such as on-chip network to overcome limitations of bus architecture. In this brief, we propose a packet-switched on-chip interconnection network architecture, through which multiple processing units of different clock frequencies can communicate with each other without global synchronization. The architecture is analyzed in terms of area and energy consumption, and implementation issues on building blocks are addressed for cost-effective design. A test chip is implemented using 0.38-/spl mu/m CMOS technology, and measured its operation at 800 MHz to demonstrate its feasibility.

A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D rendering engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18-/spl mu/m CMOS embedded memory logic technology. Its area is 24 mm/sup 2/ and its power consumption is 120 mW.

Very Large Scale Integrated chip design consists of several steps including modeling characteristics of transistors, profiling circuit level behaviors, abstracting into gate level parameters, synthesizing logic based on timing constraints, and so on. The common concept that runs through all these sequence of design flow is modeling. Traditional VLSI design highly replies on the modeling process, and the percentage that a design chip is successful, or say yield, is determined by how much the modeling is done accurately and precisely. In order to increase the yield, designers put margins while they design. A designer assumes worst cases in design parameters like transistor speed, supply voltage, temperature, and operation frequency. Even though sufficient margin on those design parameters leads higher chance of success in chip design, the margins imply overhead on the other hand. The overhead costs additional power consumption, which should be conquered in this lowpower era. Another cause of such over-design is variable workload in a system. Most of traditional VLSI systems are designed to support the maximum possible workload and the system becomes to have headroom in terms of performance when the workload is not that high. Modern VLSI designs deploy the concept of adaptive control schemes to manage the costs caused by the over-designs. A chip embeds transistor speed meter, and temperature sensors to monitor actual environment that the chip is operating in, and adjusts the margins to be minimal in order to minimize the additional cost. According to the workload offered to the system, the system controls its supply voltage dynamically thus the system keeps its performance just as enough. In this chapter, we introduce the design cases that use adaptive control schemes to manage the overhead while reducing power consumption. One another factor causing over-design is uncertainty, which is emerged in recent VLSI design area. Huge complexity of system-on-chips and ever shrinking transistor size has brought the uncertainty issue in modern VLSI design. One example is clock synchronization issue. As the clock frequency goes beyond Giga-hertz, the chip area is no longer bounded within a single clock cycle, thus, clock synchronization in a chip became extremely challenging, and even impossible to achieve. The terminology, Network-on-Chip has begun to widely spread in the VLSI design field as a chip becomes a set of systems interconnected through a network. In such a big system, transmitting and receiving data signals involves timing uncertainty because it is no longer a synchronous system. Such uncertainty incurs

An on-chip interconnect is implemented with 3Gbps/wire bandwidth performance with 8:1 serialization scheme. Such high-speed serialization is achieved using a novel serialization scheme, wave-front-train. In order to apply such high-speed link technique to network-on-chip channels, three adaptive control schemes are used: supply voltage dependent reference voltage control, phase compensation scheme with self-calibrating function, and adaptive bandwidth control. The chip is fabricated using 0.18/spl mu/m CMOS technology.

A structured packet-switched networks-on-chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. The chip integrates multiprocessors, multiple memories, and other heterogeneous intellectual properties and interconnection with 51mW and 1.6GHz on-chip networks. The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization. A network-in-package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications

An adaptive network-on-chip (NoC) is implemented with self-calibration and dynamic bandwidth control. The chip calibrates skew between clock domains automatically for reliable mesochronous communication. Link bandwidth is controlled adaptively according to network traffic for energy-efficient packet transmission. A new on-chip serialization scheme, wave-front train (WAFT), is used in the NoC chip to realize high-performance serial link with minimum overhead. The chip is fabricated using 0.18/spl mu/m CMOS technology. The overall network and WAFT operations are successfully measured at 1.2Gb/s and 3Gb/s, respectively.

A 10.8/spl times/6.0mm/sup 2/ prototype chip is implemented with a star-connected on-chip network. The chip consists of a PLL, 1KB SRAM, two 2/spl times/2 crossbar switches, Up/Down-Samplers, two off-chip gateways, and synchronizers. The on-chip network contains 81k transistors, dissipates 264mW at 2.3V and 800MHz, and provides 1.6GB/s per port and 12.8GB/s aggregated bandwidth, supporting plesiochronous communication without global synchronization.

An embedded 3D graphics rendering engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.

The digital TCXO (DTCXO) has been studied extensively because of its high frequency accuracy and rapid start-up time. The value of compensation capacitance used in the DTCXO is stored in ROM or calculated by computing circuit. In this work, ROM and computing circuit are integrated together to obtain the merit of both schemes; accurate value and high resolution of compensation capacitance, respectively. The DTCXO contains a temperature sensor, A/D converter, controller, EEPROM, capacitor bank, and oscillator. The oscillation frequency can be pulled from /spl plusmn/25 ppm to the required frequency with sub-ppm accuracy. The maximum power consumption of the total chip is 6.6 mW at 3.3 V. The chip, die size of 9mm/sup 2/, is fabricated by a 0.5 /spl mu/m CMOS technology.