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This paper presents a 4-b phase-domain analog-to-digital converter (ADC) that utilizes the time-domain reference generation scheme for low-power operation. Rather than prior arts that rely on power-hungry resistive/current combiners or the IQ-assisted binary-search algorithm with large power T&H circuits for the reference generation, this design benefits from the fully dynamic power characteristic of the time-domain operation, thus leading to an energy-efficient phase ADC design. By introducing several on-chip calibration techniques, the design achieves good robustness with the proposed time-domain operation. The prototype is fabricated in the standard 65-nm CMOS technology, achieving an ENOB of 3.42 bits at 1 MS/s with near Nyquist input, while dissipating $7~\mu \text{W}$ from a 1-V supply. It leads to a 1.36-pJ/conversion-step Walden Figure of Merit at Nyquist input (FoM@Nyquist). [ABSTRACT FROM AUTHOR]

This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades off by using the passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: noise and matching limited sampling. Moreover, we propose a boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step. [ABSTRACT FROM AUTHOR]