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This brief presents a high efficiency fully integrated high-voltage (HV) pulse driver in standard CMOS. Powered by a standard I/O DC voltage of 2.5 V, the proposed system employs an optimized 4-stage cross-coupled switched-capacitor voltage multiplier (SCVM) together with an on-chip HV output driver to generate HV pulses of >10 V. We propose an area-efficient HV output driver stage to reach up to 12% total active area reduction when compared with the conventional implementation while maintaining the low static power characteristics. We also present a synchronous charge compensation (SQC) technique to alleviate the loading-dependent signal distortion through reducing the HV rail voltage droop and improving the HV pulse settling time during the driver output transitions. Fabricated in 65-nm bulk CMOS, the chip prototype can successfully generate HV pulses from 250 kHz to 1 MHz with a 15 pF load while ensuring no device breakdown. Measurement results demonstrate a peak SCVM power conversion efficiency (PCE) of 50% and an overall driving efficiency of 12.25%. The chip prototype attains a $\sim 2\times $ faster output pulse transition speed compared with the state-of-the-art. [ABSTRACT FROM AUTHOR]

This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18-\mum CMOS process with analog options, the 1.1-mm^2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -\6 dBm and a sensing inaccuracy of \pm\0.8^\circC (3 \sigma inaccuracy) over operating temperature range from -\20^\circC to 30^\circC with one-point calibration. [ABSTRACT FROM PUBLISHER]