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The predicting correction technique (PCT) is proposed to achieve an adaptive on-time control for ripple-based buck converters. The switching frequency $f_{{\rm SW}}$ variation is suppressed when the PCT technique considers complete parasitic resistances of the components and devices. Even without extra clock-controlled circuits and current sensing circuits, the buck converter operates with a nearly constant $f_{{\rm SW}}$ over a wide load range. Parasitic resistances almost cause no influence and restriction on $f_{{\rm SW}}$. Only input voltage is used to predict the adaptive on-time. Measurement results show only 0.32% in $\Delta f_{{\rm SW}}/f_{{\rm SW}}$ and 5.7 kHz/A in $\Delta f_{{\rm SW}}/\Delta I_{{\rm LOAD}}$ in case of 1.4 A load current change and $f_{{\rm SW}}$ is 2.5 MHz. Consequently, a pseudo-constant $f_{{\rm SW}}$ with well-defined noise spectrum strongly benefits the solution of electromagnetic interference (EMI) for system-on-a-chip (SoC) applications. [ABSTRACT FROM AUTHOR]

This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-µm standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/µs saved 53% power. [ABSTRACT FROM AUTHOR]

This paper presents a technique to reduce the quantization error in fractional division for a wideband fractional-N frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as the phase-to-pulse converter, the quantization error can be much smaller than the one by conventional sigma-delta modulated multi-modulus divider. With small quantization error, a dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip was implemented with 0.18-\mu\ m CMOS. The synthesizer consumes 19 mA from a 1.8 V supply. With 1 MHz closed-loop bandwidth, the in-band noise is - \ 98~dBc/\ Hz and the 3 MHz offset noise is - \ 122~dBc/\ Hz for a 1.8 GHz output. The output exhibited 27 dB phase noise reduction compared to the generic sigma-delta structure. The settling time is 2 \mu\ s under a 35 MHz frequency step. [ABSTRACT FROM PUBLISHER]