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Your search keyword '"Shen, Linxiao"' showing total 2 results
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2 results on '"Shen, Linxiao"'

1. Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques.

Author

Tang, Xiyuan, Liu, Jiaxin, Shen, Yi, Li, Shaolan, Shen, Linxiao, Sanyal, Arindam, Ragab, Kareem, and Sun, Nan

Subjects
SUCCESSIVE approximation analog-to-digital converters, ANALOG-to-digital converters, DIGITAL-to-analog converters, ENERGY consumption, DESIGN techniques, DESIGN
Abstract

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

Published
2022
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2. A Second-Order Purely VCO-Based CT $\Delta\Sigma$ ADC Using a Modified DPLL Structure in 40-nm CMOS.

Author

Zhong, Yi, Li, Shaolan, Tang, Xiyuan, Shen, Linxiao, Zhao, Wenda, Wu, Siliang, and Sun, Nan

Subjects
ANALOG-to-digital converters, SUCCESSIVE approximation analog-to-digital converters, VOLTAGE-controlled oscillators, TIME-digital conversion, PHASE-locked loops, FREQUENCY discriminators, OPERATIONAL amplifiers
Abstract

This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) $\Delta \Sigma $ analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. An array of phase/frequency detectors (PFDs) is used to relax the requirement on the VCO center frequency and thus reduces the VCO power and noise. The proposed architecture also realizes an intrinsic tri-level data-weighted averaging (DWA). A prototype chip is fabricated in a 40-nm CMOS process. The proposed ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 69.4 dB over 5.2-MHz bandwidth, while operating at the 260 MS/s and consuming 0.86 mW from a 1.1-V supply. [ABSTRACT FROM AUTHOR]

Published
2020
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