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Wafer map defect pattern recognition provides useful clues to yield learning. However, most wafer maps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Especially, recognizing scratch and line types of defect patterns is challenging for process and test engineers. It takes a lot of manpower to identify such patterns, as hidden defective dies may exist on the scratch contour and become discontinuity points. Hidden scratch defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in scratch patterns and mark them as faulty. As a result, the quality and reliability of products is significantly improved and cost of final test is reduced. In this article, we propose a systematic methodology to search for potential hidden scratch/line defects in wafers. A five-phase method is developed to enhance wafer maps such that automatic hidden scratch defect pattern recognition can be carried out with high accuracy. Experimental results show the proposed method achieves higher than 89% recognition rate for scratch/line patterns, and higher than 94% for all common wafer defect pattern types. [ABSTRACT FROM AUTHOR]