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The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device. [ABSTRACT FROM AUTHOR]

This article presents the design of an LC-Tank voltage-controlled oscillator (VCO) for space and high-energy physics (HEP) applications. The main goal of this work is to design a radiation-hard oscillator to be integrated into a phase-locked loop (PLL), compliant with (but not limited to) SpaceFibre protocol requirements, which is able to support the 6.25 GHz frequency. The full custom schematic and layout of the LC-VCO are reported in this work. The LC-VCO is implemented in a commercial 65 nm CMOS technology, and its electrical characterization highlights a tuning range (TR) from 5.4 to 6.8 GHz. An experimental chip was fabricated and irradiated with X-rays up to 1 Grad (SiO2) total ionizing dose (TID) level at CERN facility. The TID experiment and measurement results are analyzed and discussed. The LC-VCO shows a frequency degradation of 2.54% and a 3.34% increment in phase noise at 1 Grad TID. The results achieved are of interest for both space and HEP applications. [ABSTRACT FROM AUTHOR]

Optical links are rapidly becoming pervasive in the readout chains of particle physics detector systems. Silicon photonics (SiPh) stands as an attractive candidate to sustain the radiation levels foreseen in the next-generation experiments, while guaranteeing, at the same time, multi-Gb/s and energy-efficient data transmission. Integrated electronic drivers are needed to enable SiPh modulators' deployment in compact on-detector front-end modules. A current-mode logic-based driver harnessing a pseudo-differential output stage is proposed in this work to drive different types of SiPh devices by means of the same circuit topology. The proposed driver, realized in a 65 nm bulk technology and already tested to behave properly up to an 8 MGy total ionizing dose, is hybridly integrated in this work with a lumped-element Mach–Zehnder modulator (MZM) and a ring modulator (RM), both fabricated in a 130 nm silicon-on-insulator (SOI) process. Bit-error-rate (BER) performances confirm the applicability of the selected architecture to either differential and single-ended loads. A 5 Gb/s data rate, in line with the current high energy physics requirements, is achieved in the RM case, while a packaging-related performance degradation is captured in the MZM-based system, confirming the importance of interconnection modeling. [ABSTRACT FROM AUTHOR]