Search

This brief presents a power- and area-efficient forwarded-clock (FC) receiver with a delay-locked loop (DLL)-based self-tracking loop for unmatched memory interfaces. In the proposed FC receiver, the self-tracking loop is composed of two-stage cascaded DLLs to support a burst mode. The proposed scheme compensates for a delay drift neither by relying on data (DQ) transitions nor by re-training but with a write training of the memory controller to fine-tune a data strobe (DQS) path delay through DLLs. The proposed FC receiver is fabricated in the 65-nm CMOS technology and the active area including 4 DQ lanes is 0.0329 mm2. After the write training is completed at supply voltage of 1 V, the measured timing margin remains larger than 0.31 UI when the supply voltage drifts in the range of 0.94 V and 1.06 V from the training voltage, 1 V. At the data rate of 6.4 Gb/s, the proposed FC receiver achieves an energy efficiency of 0.45 pJ/bit.

This paper presents a data (DQ) receiver for HBM3 with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift. The self-tracking loop achieves low power and small area by utilizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage difference and detects the phase skew from the voltage difference. An offset calibration scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing circuits by taking advantage of the write training of HBM. Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4.8 Gb/s and occupies 0.0056 mm2. The experimental results show that the DQ receiver operates without any performance degradation under ${a}\pm 10$% supply variation.

A feedback edge combiner is proposed for the duty-cycle corrector (DCC) of a delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge combiner generates the rising edge of a DCC output at the rising edge of an input clock. It generates the falling edge of the DCC output at the rising edge of a feedback clock that is a half-period-delayed signal of the DCC output. A dual-delay-line digitally controlled delay line (DCDL) is used for seamless boundary switching. The chip area of the DCDL is reduced by around 46% by employing the architecture of two short coarse delay lines followed by a fine phase mixer (FPM) and a long coarse delay line in series instead of the architecture of two long coarse delay lines followed by an FPM. The measurements on the chip fabricated in the 65-nm CMOS show the allowed input duty cycle in the range from 20% to 80%; root-mean-square and peak-to-peak jitters of 2.69 and 14.0 ps, respectively, at 2 GHz and 1.2 V; and the operating frequency range from 0.12 to 2.0 GHz at 1.2 V. The measured power consumption is 3.3 mW/GHz at 1.2 V. The chip area is 0.059 mm 2.

A single-ended transmitter (Tx) is proposed to compensate for the crosstalk-induced jitter (CIJ) of coupled microstrip lines by subtracting a mimicked crosstalk waveform from data signal at Tx during the data transition time, depending on the data transition of an adjacent line. Since the CIJ component is proportional to the time derivative of data signal, the mimicked crosstalk waveform subtracted at Tx cancels the CIJ at receiver (Rx) for the linearly changing data signal with time. As a by-product, this scheme reduces ISI at Rx. The Tx chip in a 0.13-μm CMOS process reduces the total Rx jitter by 96 ps (69%) at 7.2 Gbps (4-in channels) and by 120 ps (72%) at 6 Gbps (8-in channels).

By using the data timing control at transmitter (TX) side, the crosstalk-induced jitter (CIJ) is compensated in a 4 Gbps single-ended transmitter with 3-bit parallel data. CIJ is induced by the propagation velocity difference between the signal modes of parallel transmission lines. This velocity difference was compensated for by sending data early or late at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 mum CMOS process. The parallel transmission lines used in the measurements are 4-inch long, have the minimum-allowed spacing between transmission lines to maximize CIJ. CIJ was measured to be reduced by about 50% from 53 ps to 27 ps at 4 Gbps excluding the random jitter component of 72 ps added at the TX side. The scheme used in this work can be expanded to more than three transmission lines.

By using the data timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver (RX) at the same time. This transmitter is implemented by using the delay block with low jitter and a 3:1Mux to select one CLKT of the generated three different sampling CLKD, in advance. The TX is implemented by using a 0.18 μm CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps.

A single-ended transmitter eliminates the crosstalk-induced jitter at receiver by controlling the slew rates of the signal at transmitter for the even and odd modes of two parallel coupled microstrip lines. The transmitter chip in a 0.18 µm CMOS process reduces the total RX jitter by about 38 ps (53%) for the data rates from 2.6 to 5 Gbps, and increases the horizontal eye-opening (BER < 1E-12) by about 21% at 5 Gbps.