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A time-to-digital converter (TDC) often consists of sophisticated, multilevel, subgate delay structures, when time intervals need to be measured precisely. The resolution improvement is rewarding until integral nonlinearity (INL) and random jitter begins to limit the measurement performance. INL can then be minimized with calibration techniques and result postprocessing. The TDC architecture based on a counter and timing signal interpolation (the Nutt method) makes it possible to measure long time intervals precisely. It also offers an effective means of improving precision by averaging. Traditional averaging, however, demands several successive measurements, which increases the measurement time and power consumption. It is shown here that by using several interpolators that are sampled homogeneously over the clock period, the effects of limited resolution, interpolation nonlinearities, and random noise can be markedly reduced. The designed CMOS TDC utilizing internal systematic sampling technique achieves 3.0-ps root mean square (RMS) single-shot precision without any additional calibration or nonlinearity correction.

A pulse width-controlled CMOS pulser for a semiconductor laser diode (LD) and a time-gated time-resolved 8×4 single-photon avalanche diode array with a time-to-digital converter (TDC) were designed on a single integrated circuit and simulated by using a 150 nm technology. The pulse width of the driving current can be adjusted from 0.5 ns to 2.5 ns with a resolution of 100 ps. The start time of the time-gating can be adjusted over a dynamic range of 4.8 ns with a resolution of 100 ps and, furthermore, a 121 ps time-gating can be achieved. The returning photons are detected by the TDC with a resolution of 50 ps and stored to the 128 14-bit counters for merging to the distribution time-of-flight histogram. The average power consumption of the whole system was 377 mW at a repetition rate of 10 MHz.

Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 μm CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB., FRCT - Fundo Regional para a Ciência e Tecnologia(PDE/BDE/114562/2016)

Multi Digital Silicon Photon Multipliers (MDSiPM), as image sensors, are utilized to calculate and estimate the properties of the incident light. These properties include spatial location of hits, intensity or number of photons and time of arrival. Some characteristics can be more important than others depending upon the problem at hand. Among endless applications where MDSiPMs are used for, Positron Emission Tomography and LiDAR are the two that this thesis is focused on. Positron Emission Tomography is an imaging technique to monitor functional information about tissue and organs, including early cancer lesions. This constitutes the main difference with structural techniques such as radiography, where, by means of Xrays, a projection of a section of the body under test is obtained.

Many industrial and scientific applications, ranging from 3D imaging (such as LIDAR, surveillance, object tracking) to Time Correlated Single Photon Counting (TCSPC), require the ability to perform time-resolved detection of weak light signals, down to single-photon level. Single-Photon Avalanche Diodes are solid-state detectors capable of single-photon sensitivity in the visible and near-infrared wavelength regions and compatible with standard silicon processes. This demand driven the development of low cost, large size CMOS SPAD imagers. In this work we present the design and characterization of a time-gated 32x32 SPAD image sensor fabricated in a 0.16 μm BCD (Bipolar-CMOS-DMOS) technology. The sensor is based on an innovative 16x16 macropixel structure, each composed by four SPADs with independent sensing front-end and event counters, plus a shared Timeto- Digital Converter (TDC). This approach enables higher fill-factor (9.6% with a pixel pitch of 100 μm) by sharing the costly (in terms of area) TDC resource, as well as reduced power dissipation. The imager provides simultaneous photon-timing and photon-counting data and features a 12 bit, 75 ps bin width TDC, which can perform one conversion per each gate window, with up to 62 windows per data readout frame. Two main operation modes are available: a single-photon mode, where an arbitration circuit within the macropixel is used to share the TDC among the 4 SPADs, but with no loss of X-Y resolution (i.e. keeping information about the triggered SPAD); and a two-photon-coincidence mode, where the TDC performs a conversion only if two SPADs of the macropixel are triggered within a preset coincidence window. Lastly, the sensor features multiple readout modes, with varying amount of output data, in order to fit different end-user applications. The imager is capable of 100 kfps (frames per second) in full readout mode, and up to 400 kfps in a reduced data set mode.

The present work describes a new channel architecture suited to reading out Silicon Photomultipliers (SiPM). The aim is to develop a multichannel Application-Specific Integrated Circuit (ASIC) in a standard CMOS 130 nm technology that achieves excellent timing accuracy while fully exploiting the dynamic range of large area SiPMs. The sensor is AC-coupled to the differential front-end, which features two separated timing and charge signal processing paths. The first one exploits a differential input current-mode preamplifier and an embedded Time-to-Digital Converter (TDC) that exhibits a 10 ps binning. Accurate timing and low jitter are also attained by means of a high-speed discriminator with threshold adjustable in small steps just above the baseline, which operates on the very steep edge of the output signal produced by the preamplifier. The charge measurement signal path is based on an active-RC integrator, a peak detector and an Analog-to-Digital Converter (ADC). Operating the front-end at 1.2 V supply voltage, with a power consumption of 10 mW, a simulated Single-Photon Time Resolution (SPTR) of 78 ps at Full-Width Half Maximum (FWHM) is achieved, linearly covering an input dynamic range of 1280 pC that corresponds to ~ 8000 photoelectrons with a SiPM gain of ~ 106.

We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing performance evaluation, and includes all features necessary for the various operation modes, as well as the migration to the TSMC 130 nm CMOS technology. We present the TDC design with the emphasis on added features and performance optimization. Tests of the timing performance demonstrate that this ASIC meets the design specifications. The TDC has a bin size of about 780 ps, and a timing bin variations within 40 ps for all 24 channels with leading and trailing edge digitization, while the power consumption has been limited to 250 mW, corresponding to a consumption of about 5.2 mW per edge measurement., Comment: 9 pages, 7 figures

This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. The design and simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.

The adoption of the digital/time converter (DTC) circuit has improved the performance of ΔΣ fractional-N phase-locked loops (PLLs). Accurate cancellation of ΔΣ quantization error via the DTC requires an automatic calibration made by an LMS loop. A high-order ΔΣ speeds up calibration convergence and improves PLL spectral purity, though at the price of larger quantization error and wider DTC range. To overcome this problem, we propose an innovative parallel segmentation scheme which reduces the range of quantization error without compromising spectral purity and convergence speed. The effectiveness of the proposed segmentation scheme is demonstrated via behavioral-level simulations of a digital PLL and compared to the conventional cascaded segmentation scheme.

This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively.

The demands for an ever higher data rate and a more varied functionality at minimal cost and power consumption have been the driving force behind most innovations in wireless communication systems. Intensive efforts have been made to develop Radio Frequency (RF) Integrated Circuits (ICs) and systems using low-cost Complementary Metal Oxide Semiconductor (CMOS) processes. In radio transceivers for wireless systems, the commonly used frequency synthesizer based on a Phase Locked Loop (PLL) is a crucial building block. In fact, the frequency synthesizer is responsible for the generation of high-purity RF signals utilized to shift up and down in frequency the information content of the transmission, and, as such, determines the performance of the whole transceiver to a large extent, while it is responsible for a large portion of the power consumed and the area occupied by the transceiver.A state-of-the-art PLL must meet stringent requirements on signal purity, while dissipating increasingly lower power to lengthen battery lifetime and being capable of operating at the very low supply voltages required by modern CMOS processes. Furthermore, such a PLL should occupy a small area and coexist with very complex digital systems, which are responsible for the generation of extensive switching noise.With the extraordinary pace of CMOS technology scaling and the attending increase in integration density, conventional analog designs are giving way to digital counterparts, which much better exploit the new silicon ecosystems. The foremost example of this momentous trend is probably the PLL, where the Digital Phase Locked Loop (DPLL) can exploit all the advantages, in terms ofprogrammability, reconfigurability, and adoption of advanced adaptive digital algorithms for the correction of PLL non-idealities, that are beyond the reach of the analog PLL.In this dissertation, several IC design techniques are demonstrated, which improve the DPLL in terms of both overall architecture and individual subblocks. One DPLL has been designed and thoroughly simulated, while one Digitally Controlled Oscillator (DCO) and another DPLL have been designed, simulated, fabricated, and tested, obtaining excellent measured performance

We report on the design and characterization of a novel time-resolved image sensor fabricated in a 130 nm CMOS process. Each pixel within the 32x32 pixel array contains a low-noise single-photon detector and a high-precision time-to-digital converter (TDC). The 10-bit TDC exhibits a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential non-linearity (DNL) and integral non-linearity (INL) were measured at +/- 0.4 and +/- 1.2 LSBs, respectively. The pixel array was fabricated with a pitch of 50 mu m in both directions and with a total TDC area of less than 2000 mu m(2). The target application for this sensor is time-resolved imaging, in particular fluorescence lifetime imaging microscopy and 3D imaging. The characterization shows the suitability of the proposed sensor technology for these applications.

Detecting and counting single photons is useful in an increasingly large number of applications. Most applications require large formats, approaching and even far exceeding 1 megapixel. In this thesis, we look at the challenges of massively parallel photon-counting cameras from all performance angles. The thesis deals with a number of performance issues that emerge when the number of pixels exceeds about 1/4 of megapixels, proposing characterization techniques and solutions to mitigate performance degradation and non-uniformity. Two cameras were created to validate the proposed techniques. The first camera, SwissSPAD, comprises an array of 512 x 128 SPAD pixels, each with a one-bit memory and a gating mechanism to achieve 5ns high precision time windows with high uniformity across the array. With a massively parallel readout of over 10 Gigabit/s and positioning of the integration time window accurate to the pico-second range, fluorescence lifetime imaging and fluorescence correlation spectroscopy imaging achieve a speedup of several orders of magnitude while ensuring high precision in the measurements. Other possible applications include wide-field time-of-flight imaging and the generation of quantum random numbers at highest bit-rates. Lately super-resolution microscopy techniques have also used SwissSPAD. The second camera, LinoSPAD, takes the concepts of SwissSPAD one step further by moving even more 'intelligence' to the FPGA and reducing the sensor complexity to the bare minimum. This allows focusing the optimization of the sensor on the most important metrics of photon efficiency and fill factor. As such, the sensor consists of one line of SPADs that have a direct connection each to the FPGA where complex photon processing algorithms can be implemented. As a demonstration of the capabilities of current lowcost FPGAs we implemented an array of time-to-digital converters that can handle up to 8.5 billion photons per second, measuring each one of them and accounting them in high precision histograms. Using simple laser diodes and a circuit to generate light pulses in the picosecond range, we demonstrate a ubiquitous 3D time-of-flight sensor. The thesis intends to be a first step towards achieving the world's first megapixel SPAD camera, which, we believe, is in grasp thanks to the architectural and circuital techniques proposed in this thesis. In addition, we believe that the applications proposed in this thesis offer a wide variety of uses of the sensors presented in this thesis and in future ones to come.

A robust TDC with 4.8 ps bin width has been designed for harsh environments and high energy physics applications. The circuit uses resistive interpolation DLL with a novel dual phase detector architecture. This architecture improves startup- and recovery speed from single event strikes without control voltage ripple trade-off and requires no off-line calibrations. A 0.43 LSB DNL has been measured at a power consumption of 4.2 mW with an extended frequency range from 0.8 GHz to 2.4 GHz. The TDC has been processed in 40 nm CMOS technology. ispartof: Journal of Instrumentation vol:10 issue:01 pages:1-8 ispartof: location:Aix en Provence, France status: published

This paper investigates the idea to construct Time-to-Digital Converter (TDC) circuits based on dynamic precharged NORA delay elements. A self-charging technique is proposed in order to accommodate the dynamic delay elements in a ring-oscillator like structure. The employ of dynamic logic allows to reduce the TDC resolution with respect to previous TDCs based on standard CMOS logic. The ring-oscillator like topology imparts a very large dynamic range to the proposed circuit. In the paper a TDC, based on a Pseudo-differential topology, is presented, that is robust against PVT and mismatch variations. The TDC is fabricated in 90 nm CMOS technology, and presents a resolution of 25 ps. Experimental measurements confirm the effectiveness of the idea and show that the proposed TDCs exhibit low INL and a large dynamic-range when compared with state-of-the art circuits.

This paper presents a digital scrambling technique to improve the linearity of flash time-to-digital converters (TDCs) with sub-gate-delay time resolution. Thanks to this approach, a flash TDC using N time arbiters behaves as a quasi-stochastic TDC with an equivalent number of samples equal to N2, at the negligible area cost of doubling the number of minimum load capacitors. The concept is proved in a 65-nm CMOS technology 40MHz TDC, which achieves a 3ps resolution. The differential nonlinearity is reduced from 1LSB to less than 0.2LSB.

LinoSPAD is a reconfigurable camera sensor with a 256x 1 CMOS SPAD (single-photon avalanche diode) pixel array connected to a low cost Xilinx Spartan 6 FPGA. The LinoSPAD sensor's line of pixels has a pitch of 24 pm and 40% fill factor. The FPGA implements an array of 64 TDCs and histogram engines capable of processing up to 8.5 giga-photons per second. The LinoSPAD sensor measures 1.68 mmx6.8 mm and each pixel has a direct digital output to connect to the FPGA. The chip is bonded on a carrier PCB to connect to the FPGA motherboard. 64 carry chain based TDCs sampled at 400 MHz can generate a timestamp every 7.5 ns with a mean time resolution below 25 ps per code. The 64 histogram engines provide time-of n-arrival histograms covering up to 50 ns. An alternative mode allows the readout of 28 bit timestamps which have a range of up to 4.5 ms. Since the FPGA TDCs have considerable non-linearity we implemented a correction module capable of increasing histogram linearity at real-time. The TDC array is interfaced to a computer using a super-speed USB3 link to transfer over 150k histograms per second for the 12.5 ns reference period used in our characterization. After characterization and subsequent programming of the post-processing we measure an instrument response histogram shorter than 100 ps FWHM using a strong laser pulse with 50 ps FWHM. A timing resolution that when combined with the high fill factor makes the sensor well suited for a wide variety of applications from fluorescence lifetime microscopy over Raman spectroscopy to 3D timen-of-flight.