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Back Side Illumination (BSI) CMOS image sensors with two-layer photo detectors (2LPDs) have been fabricated and evaluated. The test pixel array has green pixels (2.2um x 2.2um) and a magenta pixel (2.2um x 4.4um). The green pixel has a single-layer photo detector (1LPD). The magenta pixel has a 2LPD and a vertical charge transfer (VCT) path to contact a back side photo detector. The 2LPD and the VCT were implemented by high-energy ion implantation from the circuit side. Measured spectral response curves from the 2LPDs fitted well with those estimated based on light-absorption theory for Silicon detectors. Our measurement results show that the keys to realize the 2LPD in BSI are; (1) the reduction of crosstalk to the VCT from adjacent pixels and (2) controlling the backside photo detector thickness variance to reduce color signal variations.

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.

Salicide is one of the indispensable techniques for high-performance logic devices and its importance increases as the device dimensions become small towards sub-100 nm and hence, the source/drain sheet resistance becomes large. TiSi2 used popularly as the silicide material has been eventually replaced by CoSi2, because of its relatively stable nature during the salicide process. For sub-100-nm technology node, CoSi2 is expected to be further replaced by NiSi. NiSi has several advantages over TiSi2 and CoSi2 for the ultra-small CMOS process. They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance, (6) smaller contact resistance for both n- and p-Si, and (7) higher activation rate of B for SiGe poly gate electrode. In this paper, NiSi salicide technology is explained.

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO/sub 2/-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated.

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO/sub 2/ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-/spl mu/m and 0.06-/spl mu/m gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-/spl mu/m gate length pMOSFETs using 1.5-nm gate SiO/sub 2/ for the first time. The normal oscillations of the 1.5-nm gate SiO/sub 2/ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-/spl mu/m gate length CMOS in terms of high-frequency, high-speed operation.

A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate; hence the doping region is fully self-aligned to the gate, and the junction capacitance can be reduced. In addition, the implantation damage in the channel is reduced. We obtained 0.25 μm gate length nMOSFETs with low noise and low power consumption by using the SADC structure. Hence, this structure is attractive for small geometry RF CMOS devices.

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-/spl mu/m RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications.

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFET's was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFET's also operated at higher speed. >

High-resistivity substrate with beyond 1000 ohm-cm realizes high performance in terms of inductor, antenna, MIM capacitor and substrate noise for high- frequency applications. However, this wafer has serious problems for mixed-signal, RF and digital circuits. Those are reduction of high resistivity during sinter process such as 400degC, larger leakage current between nwells, extreme lower snap-back voltage in latch-up behavior and higher RF noise. The RF noise is proportional to square root of Si substrate resistivity in our experience. In this paper, it is shown that these problems can be resolved by the optimum wafer fabrication process and the additional ion implantation.

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, the authors discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in Svg with technology scaling according to the ITRS roadmap based on Mikoshiba's model

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.

In this paper, we describe the high analog performance of MOSFETs and inductors on 1.7/spl mu/m ultra-thin chip with permalloy film.

Fully oxygen precipitated (FOP) wafers can suppress slip generation during the STI process and maintain high substrate resistivity. Additional boron implantation can suppress the leakage current between the adjacent wells due to shallow Xj. No effect on MOSFET characteristics by this implantation was observed. The high resistivity substrate (HRS) can provide good ESD performance and suppress the passage of high frequency signals through the substrate in resistors. Thus, HRS with FOP & additional implantation is effective for future mixed signal CMOS with RF circuits.

A non-doped selective epitaxial Si channel technique has been applied to ultra-thin gate oxide CMOS transistors with TiN and polysilicon gate electrodes, and its effect on direct-tunneling gate leakage current has been investigated. It was found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current in both the TiN and polysilicon gate electrode cases. Improved drain current drive and transconductance of the epitaxial channel MOSFETs with ultra-thin gate oxides in the direct-tunneling regime has been also demonstrated.

The concept of future scaling-down for RF CMOS technology has been investigated in terms of f/sub T/, f/sub max/, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are key parameters, especially in sub-100 nm gate length generations.

Using a newly proposed structure of the multi-via MIM capacitor, amorphous Ta/sub 2/O/sub 5/ films were investigated. Amorphous Ta/sub 2/O/sub 5/ with the proposed structure is one of the suitable combinations for the capacitors for RF analog applications.

The influence of high substrate doping on the characteristics of small-geometry n- and p-MOSFETs down to 0.1 /spl mu/m has been investigated in detail. A practical limiting impurity concentration is found to exist at around 2/spl sim/5/spl times/10/sup 18/ cm/sup -3/ depending upon the application. In addition, unusual behaviors are found in the hot carrier characteristics in the region of high doping concentration. >

We investigated the Diffused shield Under the Oxide (DUO) for the first time. DUO is an extremely shallow diffusion layer in the n-well under the field oxide. DUO can be formed by high energy implantation through the field oxide, and it can be formed by the process of the channel stop implant for MOSFETs simultaneously. Application of DUO provided a 79% improvement in Q-factor and the comparable shield effect on the n-well. This structure is one of the suitable ground shield for the spiral inductor of the rf CMOS.

We introduce a 0.12 /spl mu/m nMOS technology with multi-Vth's for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 /spl mu/m nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design. High Idrive/Ioff ratio for drain current was also realized.

Summary form only given. In order to obtain high performance analog MOSFETs, it is important to reduce gate resistance. Recently W/Ti, CoSi/sub 2/ and NiSi gate electrodes have been proposed to realize these requirements. Especially, the Co salicided T-shape gate electrode realizes easily a low gate resistance below 1.5 ohm/sq. with a small increase in the number of process steps. Additionally, short channel effects are improved because the junction depth from the Si substrate surface at deeper source and drain regions becomes shallower due to the raised source and drain. In this paper, we demonstrate the excellent analog characteristics of Co salicided T-shape gate RF CMOS technology making use of a raised gate/source/drain structure. Extremely high fmax value of 70 GHz was realized by 0.10 /spl mu/m gate length nMOSFET with low noise and low power consumption.

For low power operation in analog CMOS, a lot of attempts using new drain structures to reduce the parasitic capacitance of the source and drain junction capacitance (Cj) have been reported. However, there are not many approaches from the channel doping process. In the usual MOSFET structures, the highly doped channel implanted regions are localized under the gate by the mask used in the channel implantation step in order to reduce Cj. In this process, however, it is limited to localize the channel implanted region by the requirement of the margin for the mask misalignment in the photolithography process. Hence, Cj remained a serious problem to realize the high speed and low power operation. On the other hand, the importance of low frequency noise in RF and microwave circuit applications have been also increased. The authors show the gate length dependence of low frequency noise of MOSFETs. The spectral density of the drain current noise (SID) increases as the gate length decreased. This low frequency noise can be reduced by decreasing the dose of channel implantation process. However it is very difficult to suppress the low frequency noise with optimizing threshold voltage simultaneously. One of the reasons for higher 1/f noise at higher Vth is estimated to be due to the larger damage caused by larger dose of the channel implantation as explained later. The main object of this paper is the investigation of a self-align doped channel (SADC) structure as one of the candidates which can reduce the low frequency noise and the parasitic capacitance simultaneously. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate, hence the doped region is fully sell-aligned to the gate, and the junction capacitance can be reduced. Moreover the implantation damage in the channel is reduced. We examine the feasibility study of SADC structure and demonstrate high performance 0.25 /spl mu/m gate length nMOSEFTs with low noise and low power consumption by using SADC structure.

We introduce 0.18 /spl mu/m CMOS with multi-V/sub th/'s for mixed high-speed digital and RF-analog applications. The V/sub th/'s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFETs with zero-volt-Vth for RF analog circuits. The zero-volt-Vth MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD), the film quality is good because higher pre-heating temperature (940/spl deg/C for 30 seconds) is used in H/sub 2/ atmosphere before epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values show significantly improved performances under the low supply voltage, which is important for 0.18 /spl mu/m CMOS with low power/low supply voltage operation. Additionally, in our experiment no significant difference was observed between the reliability of gate oxide grown on bulk and the reliability of that grown on epitaxial layers. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will be effective to realize high performance and low power CMOS devices for mixed digital and RF-analog applications.

Silicided Silicon-Sidewall Source and Drain (S/sup 4/D) structures were proposed for sub-0.1 /spl mu/m gate length p-MOSFETs as the structure which can realize extremely small source and drain series resistance with small short-channel effects. By using this structure, 75 mm gate length p-MOSFETs were fabricated and very good electrical characteristics were confirmed. In this experiment, only p-MOSFETs were fabricated, but the S/sup 4/D structures are also suitable for the sub-0.1 /spl mu/m gate length CMOS devices, because, basically, the sidewall amorphous silicon is easily doped with the dopant of source and drain by source and drain implantation without prior in situ doping.

Recently, heavily nitrided NO oxynitride has been proposed as an alternative to pure oxide in order to realize high drivability and suppress a large gate leakage current (Fujiwara et al, Digest of IEDM 2000, pp. 227-30, 2000). However, in general, oxynitride has higher interface state density than that of pure oxide, and brings low frequency noise (or 1/f noise) degradation (Kimijima et al., 1999). Thus, analog characteristics under such aggressive doping conditions should be observed carefully for realization of high performance mixed analog and digital LSIs. In this paper, we report analysis of the 1/f noise degradation due to heavily nitrided NO oxynitrides and predict the interface state density value to satisfy 1999 ITRS Roadmap requirements. Additionally, a buried channel type MOSFET is proposed for suppression of the 1/f noise and f/sub T/ degradation.

High performance digital-analog mixed devices are fabricated on a high resistivity MCZ Si substrate with low oxygen in order to suppress substrate noise from digital to analog circuits. The low oxygen prevents substrate resistivity reduction due to thermal donor occurring during device fabrication process. Good characteristics of digital, analog and power amplifiers can be realized by optimizing the process of oxynitride, halo implantation and salicide. In 0.11 /spl mu/m CMOS, high drivability, that is, 770 /spl mu/A//spl mu/m for NMOS and 330 /spl mu/A//spl mu/m for PMOS was achieved at Ioff=10/sup -9/ A//spl mu/m. And fT value of 90 GHz for NMOS and 48 GHz for PMOS can be achieved. Additionally, high efficiency of 68% at 2 GHz operation can be realized in power amplifier with 0.30 /spl mu/m gate length.

We investigated the analog performance of a 0.11 /spl mu/m CMOS under a low supply voltage. In order to avoid flicker noise degradation under the low supply voltage, an epitaxial channel MOSFET without halo implantation was shown to be effective.

CMOS has been used for advanced LSIs so many years because of its excellent low-power and high-speed characteristics for highly-integrated digital circuits. For high frequency analog applications such as RF, it has not been used popularly because CMOS has been assumed to have poor capability compared with silicon bipolar and compound semiconductor devices. However, recent miniaturization of CMOS devices has significantly improved the CMOS RF characteristics. For example, typical values of f T and fmax for 0.25 μm n-MOSFETs already exceed 40 GHz, and those for 0.1 μm n-MOSFETs are more than 100 GHz. RF noise of the MOSFETs is also as good as less than 1 dB at 2 GHz operations. In this paper, CMOS technology for RF front-end circuit for mobile telecommunication devices is explained.

A high-speed 0.15 μm single-gate Co salicide CMOS technology has been demonstrated, which suppresses short channel effects in 0.15 μm buried channel pMOSFETs by optimizing the fabrication conditions of their extension region. An unloaded CMOS inverter ring-oscillator delay of 19.8 ps has been obtained. At 0.12 μm gate length, 11.4 ps gate delay was observed.

In this paper, it is shown that the 1/f noise is improved by plasma nitridation instead of NO annealing and deuterium annealing after metal formation. Additionally, dependence of the noise on distance between gate electrode and STI edge is reported for the first time.

A high performance 0.15 /spl mu/m single gate Co salicide CMOS technology have been developed by optimizing the fabrication conditions of pMOSFETs extension region. The gate delay of 19.8 psec was obtained with good suppression of short channel effect. At 0.12 /spl mu/m gate length, 11.4 psec, the fastest tpd ever reported, was observed although the short channel effects were significant at this moment. These results suggests that high performance single gate CMOS in sub-0.15 /spl mu/m region can be realized by further improving the extension conditions such as by using new doping techniques.

A nitrogen-doped NiSi technique has been developed for deep submicron CMOS. It was found that the nitrogen suppresses oxidation of the silicide film, resulting in significantly reduced roughness at the interface between silicide and the Si substrate. It was confirmed that, as a consequence, the leakage current through the silicided ultra-shallow diffused layer was significantly suppressed. The nitrogen-doped NiSi film has the advantage of containing large single crystal grains, and this reduces the resistivity of the film. The nitrogen-doped NiSi technique was used to fabricate 0.15 /spl mu/m CMOS devices, and these devices, both n- and p-MOSFETs, exhibited very high Id and gm values without leakage current.

With the expected limitations of conventional CMOS downsizing, various new structures, such as vertical and concave MOSFETs, are under serious investigation. These new types of MOSFETs have a special feature in that the channel of the MOSFETs consists of various surfaces with different crystal orientations. With thinning of the gate oxides, the substrate orientation dependence of the oxide quality becomes a major concern, because Si-SiO/sub 2/ interface quality control becomes important in terms of suppressing the tunneling leakage current and improving TDDB reliability (Sorsch et al., 1998). This paper, for the first time, reports the surface orientation dependence of the ultra-thin gate oxide properties in the direct tunneling regime. Various characteristics of the oxide and MOSFET properties were compared by fabricating direct-tunneling gate CMOS on [100]-, [100] 4/spl deg/off, and [111]-oriented Si substrates.