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This article presents the first 39-GHz phased-array transceiver (TRX) chipset for fifth-generation new radio (5G NR). The proposed transceiver chipset consists of 4 sub-array TRX elements with local-oscillator (LO) phase-shifting architecture and built-in calibration on phase and amplitude. The calibration scheme is proposed to alleviate phase and amplitude mismatch between each sub-array TRX element, especially for a large-array transceiver system in the base station (BS). Based on LO phase-shifting architecture, the transceiver has a 0.04-dB maximum gain variation over the 360° full tuning range, allowing constant-gain characteristic during phase calibration. A phase-to-digital converter (PDC) and a high-resolution phase-detection mechanism are proposed for highly accurate phase calibration. The built-in calibration has a measured accuracy of 0.08° rms phase error and 0.01-dB rms amplitude error. Moreover, a pseudo-single-balanced mixer is proposed for LO-feedthrough (LOFT) cancellation and sub-array TRX LO-to-LO isolation. The transceiver is fabricated in standard 65-nm CMOS technology with flip-chip packaging. The 8TX–8RX phased-array transceiver module 1-m OTA measurement supports 5G NR 400-MHz 256-QAM OFDMA modulation with −30.0-dB EVM. The 64-element transceiver has a EIRPMAX of 53 dBm. The four-element chip consumes a power of 1.5 W in the TX mode and 0.5 W in the RX mode. [ABSTRACT FROM AUTHOR]

This article introduces a chip-scale ultralow-power atomic clock (ULPAC) in the microwave frequency region. A new suspended quantum package architecture along with a fully integrated frequency probing and locking loop implemented in CMOS technology results in a compact package and ultralow-power consumption. In addition, dedicated low-noise magnetic field and temperature control loops are incorporated for isolating and mitigating the internal and external factors affecting the frequency stability. The output frequency of a crystal oscillator is continuously compensated and stabilized by locking to the peak of a coherent population trapping signal, thereby inheriting the superior frequency stability of the atomic resonance. The proposed ULPAC system achieves a frequency stability of $2.2 \times 10^{-12}$ at an averaging time of 105 s, while consuming 59.9 mW. The frequency probing and locking circuits implemented in a standard 65-nm CMOS process node occupy an area of 2.55 mm2. The prototype of this atomic clock occupies a volume of 15 cm3. [ABSTRACT FROM AUTHOR]

This paper presents a 60-GHz transceiver for low-power high-speed short-range wireless using the proposed binary-phase on-off keying (BPOOK) modulation scheme. The proposed BPOOK wireless transceiver transmits radio frequency (RF) signal with amplitude modulated on and off by input baseband data, and meanwhile, the phase is changing between 0° and 180°. The BPOOK transceiver achieves doubled spectral efficiency compared with OOK modulation and binary-phase-shift keying (BPSK) modulation. It also cancels the intrinsic local-oscillator feed through (LOFT) issue in the OOK modulation. The BPOOK RF signal can be demodulated by employing low-power square-law envelope detector incoherently. The transceiver is fabricated in a standard 65-nm CMOS technology. A data rate of 3.0 Gb/s is achieved while consuming a power of 100 mW from 1-V supply. The incoherent receiver has a sensitivity of −46 dBm. The core area of the transceiver is 1.56 mm2. [ABSTRACT FROM AUTHOR]