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This letter presents an ultrawideband 7-bit digital-step attenuator (DSA). Capacitive compensation technique is utilized to improve the amplitude and phase accuracy and enable wideband operation. The attenuator is implemented in a 55-nm CMOS process and occupies 0.044-mm² core area. It demonstrates a 15.9-dB attenuation range with a 0.125-dB step size. The measured insertion loss (IL) is 2.7-6.6 dB at dc-28 GHz and the rms amplitude and phase errors of four measured chips are

This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The $\pi $ -type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole–zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5–8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm2 core area and consumes negligible power.

This paper presents a 4-element 7.5-9 GHz phased array receiver with 1-8 concurrent beams in a 65-nm CMOS technology. All the elements are fully-connected to each output beam using 32 phase shifters and 8 active combiners. The current-starving gm-based phase shifter with 6-bit phase resolution achieves

This paper presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy from DC to Ka band, designed and fabricated in a 55-nm CMOS technology. Staggered π-type and bridge-T type stages with capacitive compensation are proposed to minimize amplitude and phase errors, and to extend its operation bandwidth. The chip demonstrates a 32.385-dB attenuation range with a 0.255-dB attenuation step and a 3.5-8.4 dB IL across DC to 32 GHz. The measured RMS amplitude and phase errors are below 0.32 dB and 5.33° respectively. The die occupies 0.054 mm2(0.632 mm × 0.086 mm) core area and consumes negligible power. To the best of our knowledge, this work shows the smallest area and the widest bandwidth among the reported switch type attenuators.