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This paper reports a novel oscillator circuit topology based on a transformer-coupled p-network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root-locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed-form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer-coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. [ABSTRACT FROM AUTHOR]

This paper presents a 67GHz LC oscillator exploiting a three-spiral transformer and implemented in 65nm bulk complementary metal-oxide-semiconductor technology by STMicroelectronics. The three-spiral transformer allows operating with a lower voltage supply, still obtaining good phase noise performance, and achieving a compact design. Measured performances when supplied with 1.2 V are: oscillation frequency of 67 GHz, phase noise ( PN) equal to −96 dBc/Hz at 1 MHz frequency offset from the carrier, power consumption ( PC) equal to 19.2 mW and figure of merit ( FOM) equal to −179.7 dB/Hz. Measured performances when supplied with 0.6 V are: oscillation frequency of 67 GHz; PN equal to −88.7 dBc/Hz at a 1 MHz frequency offset from the carrier; PC equal to 3.6 mW and FOM equal to −179.7 dB/Hz. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The potential of active inductors (AIs) has been often reduced by lack of accurate design methodologies and limitations due to the inherent noise sources. This paper deals with these two open issues for a high-frequency CMOS AI characterized by high-quality factor, low-power consumption, and low noise. First, it reports an effective design methodology for the implementation of high-frequency CMOS AIs with a high-quality factor. In particular, it shows how, through an advanced small-signal circuit model, to carry out an accurate and reliable design at high frequency (over 10 GHz) in modern nanoscale CMOS process. The design methodology is validated through cases of study at 13 GHz implemented in a standard 90-nm CMOS process and characterized experimentally. The results show that the AI exhibits an equivalent inductance close to 3.2 nH with an associated quality factor close to 200. After, it reports a noise analysis. It shows that the AI exhibits a very low level of noise, enabling its application to the implementation of high-quality factor low-noise LC tank in high-frequency building blocks of radio frequency front-ends. The results show that the AI exhibits a noise power spectral density lower than −150 dBm/Hz. [ABSTRACT FROM AUTHOR]

Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nanoscale CMOS LC oscillators. [ABSTRACT FROM AUTHOR]

A fully differential analog multiplier for wideband operations is presented. The circuit consists of a p-MOSFET common-gate differential pair input stage for wideband impedance matching, a p-MOSFET Gilbert quad as a multiplier stage, and active loads. The circuit has been designed and fabricated in 90-nm CMOS. The test-chip area is 560 \times 700\ \mu\m^2. The overall power consumption is 3.7 mW from a 1.2-V power supply. In the case of input monocycle pulses with duration time of 700 ps, the measurements show an input–output energy ratio equal to 2, a conversion gain of 12.7 dB at intermediate frequencies in the range of 0.001–10 MHz for input tones in the range of 2–4 GHz, a noise figure of 14.4 dB (minimum) and compression points of -3.5 and -2 dBm for the two inputs. The performance of the proposed multiplier favorably compares with the state of the art. [ABSTRACT FROM PUBLISHER]

A high gain W-band low noise amplifier for radiometric applications in 28 nm bulk CMOS technology is presented. Pads, inductors, capacitors and coplanar waveguides have been custom designed. The parasitic effects of the transistor layout have been evaluated by means of electromagnetic simulations and calculations based on data reported in the design rule manual of the technology. The amplifier consists of six cascode stages with input, output and interstage conjugate matching for maximum power transfer. Measurement results show a peak gain of 32 dB and a noise figure of 5.3 dB at 91 GHz. [ABSTRACT FROM PUBLISHER]

This letter presents a millimeter-wave active inductor circuit designed and fabricated in 65 nm bulk CMOS technology. The measurement results show an equivalent inductance of 133 pH with a quality factor exceeding 400 at 50 GHz, demonstrating experimentally for the first time the possibility to implement high-Q active inductors in CMOS technology operating at the mm-waves. [ABSTRACT FROM PUBLISHER]

A 13 GHz active inductor LC voltage controlled oscillator (VCO) has been realized in 90 nm CMOS technology by ST-Microelectronics. The VCO consists of two complementary cross-coupled pairs, an active LC tank implemented by means of a differential high-Q low-noise active inductor and two p-MOSFET varicaps, and an output buffer stage. The measurements show a phase noise of -105.25 ~dBc/Hz at 1 MHz frequency offset. The current consumption of the VCO core and differential boot-strapped inductor amount to 0.7 and 1.8 mA, respectively, from a 1.2 V supply voltage. [ABSTRACT FROM PUBLISHER]