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Perpendicular-anisotropy magnetic tunnel junction (MTJ) is one of the most promising candidates to build hybrid logic-in-memory architecture, because of its nonvolatility, infinite endurance, and 3-D integration with a CMOS technology. A novel magnetic full-adder (MFA) based on this architecture is proposed, with MTJs switched by spin-Hall-assisted spin-transfer torque (STT). Owing to the assistance of spin-Hall effect (SHE), MTJ switching time can significantly be reduced, and high operation frequency can be achieved. Moreover, the endurance of oxide barrier is largely enhanced as the requirement of lower write voltage. Using an industrial CMOS 28 nm design kit and a physics-based three-terminal spin-Hall-assisted STT-MTJ model, functionality and performance of the proposed MFA have been simulated and validated. A 1 ns STT current pulse assisted by 0.35 ns SHE current pulse is sufficient to switch the MTJ configuration. When compared with the previous MFAs based on STT-MTJ, the proposed MFA achieves 38% less operation time and 31% less power consumption to perform read and write operations. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM’s wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]