Search

This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano-scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper reports the analyses of three techniques for phase noise reduction in the complementary metal-oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28-nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1-MHz frequency offset for an oscillation frequency of 10 GHz. © 2015 The Authors International Journal of Circuit Theory and Applications Published by John Wiley & Sons Ltd. [ABSTRACT FROM AUTHOR]

The potential of active inductors (AIs) has been often reduced by lack of accurate design methodologies and limitations due to the inherent noise sources. This paper deals with these two open issues for a high-frequency CMOS AI characterized by high-quality factor, low-power consumption, and low noise. First, it reports an effective design methodology for the implementation of high-frequency CMOS AIs with a high-quality factor. In particular, it shows how, through an advanced small-signal circuit model, to carry out an accurate and reliable design at high frequency (over 10 GHz) in modern nanoscale CMOS process. The design methodology is validated through cases of study at 13 GHz implemented in a standard 90-nm CMOS process and characterized experimentally. The results show that the AI exhibits an equivalent inductance close to 3.2 nH with an associated quality factor close to 200. After, it reports a noise analysis. It shows that the AI exhibits a very low level of noise, enabling its application to the implementation of high-quality factor low-noise LC tank in high-frequency building blocks of radio frequency front-ends. The results show that the AI exhibits a noise power spectral density lower than −150 dBm/Hz. [ABSTRACT FROM AUTHOR]

An ultra wideband (UWB) system-on-chip radar sensor for respiratory rate monitoring has been realized in 90 nm CMOS technology and characterized experimentally. The radar testchip has been applied to the contactless detection of the respiration activity of adult and baby. The field operational tests demonstrate that the UWB radar sensor detects the respiratory rate of person under test (adult and baby) associated with sub-centimeter chest movements, allowing the continuous-time non-invasive monitoring of hospital patients and other people at risk of obstructive apneas such as babies in cot beds, or other respiratory diseases. [ABSTRACT FROM PUBLISHER]

A fully differential analog multiplier for wideband operations is presented. The circuit consists of a p-MOSFET common-gate differential pair input stage for wideband impedance matching, a p-MOSFET Gilbert quad as a multiplier stage, and active loads. The circuit has been designed and fabricated in 90-nm CMOS. The test-chip area is 560 \times 700\ \mu\m^2. The overall power consumption is 3.7 mW from a 1.2-V power supply. In the case of input monocycle pulses with duration time of 700 ps, the measurements show an input–output energy ratio equal to 2, a conversion gain of 12.7 dB at intermediate frequencies in the range of 0.001–10 MHz for input tones in the range of 2–4 GHz, a noise figure of 14.4 dB (minimum) and compression points of -3.5 and -2 dBm for the two inputs. The performance of the proposed multiplier favorably compares with the state of the art. [ABSTRACT FROM PUBLISHER]

A high gain W-band low noise amplifier for radiometric applications in 28 nm bulk CMOS technology is presented. Pads, inductors, capacitors and coplanar waveguides have been custom designed. The parasitic effects of the transistor layout have been evaluated by means of electromagnetic simulations and calculations based on data reported in the design rule manual of the technology. The amplifier consists of six cascode stages with input, output and interstage conjugate matching for maximum power transfer. Measurement results show a peak gain of 32 dB and a noise figure of 5.3 dB at 91 GHz. [ABSTRACT FROM PUBLISHER]

This letter presents a millimeter-wave active inductor circuit designed and fabricated in 65 nm bulk CMOS technology. The measurement results show an equivalent inductance of 133 pH with a quality factor exceeding 400 at 50 GHz, demonstrating experimentally for the first time the possibility to implement high-Q active inductors in CMOS technology operating at the mm-waves. [ABSTRACT FROM PUBLISHER]

A 13 GHz active inductor LC voltage controlled oscillator (VCO) has been realized in 90 nm CMOS technology by ST-Microelectronics. The VCO consists of two complementary cross-coupled pairs, an active LC tank implemented by means of a differential high-Q low-noise active inductor and two p-MOSFET varicaps, and an output buffer stage. The measurements show a phase noise of -105.25 ~dBc/Hz at 1 MHz frequency offset. The current consumption of the VCO core and differential boot-strapped inductor amount to 0.7 and 1.8 mA, respectively, from a 1.2 V supply voltage. [ABSTRACT FROM PUBLISHER]