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This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs. [ABSTRACT FROM AUTHOR]

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter. [ABSTRACT FROM AUTHOR]

This paper presents designs of ternary and quaternary up/down counters of single and multiple digits using CNTFET. The proposed counters have a special feature of counting in dual mode; up counting and down counting which makes these designs distinct from other existing designs. The proposed counters are designed using ternary/quaternary D flip-flops and a dynamic successor-predecessor circuit. The D flip-flops are built using standard ternary/quaternary inverters (STI/SQI) with an additional reset feature. The proposed dynamic successor-predecessor circuit has the capability of acting either as a successor or as a predecessor circuit based on a control signal. Counter circuits of multiple digits have been achieved with the help of a few additional transistors along with the single-digit counter circuits. All the proposed designs have been simulated in HSPICE using Stanford University's 32 nm CNTFET model and simulation results have been noted. When compared with existing designs, the proposed designs show improvements in power and energy efficiency. [ABSTRACT FROM AUTHOR]