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Wireless 3-D network-on-chips (NoCs) with inductive-coupling ThruChip interfaces provide a large degree of flexibility for customizing the number of arbitrary chips in a package after chips have been fabricated. To simplify the vertical communication interfaces, static time division multiple access (TDMA) is used for the vertical broadcast buses, while arbitrary or customized topologies can be used for the intrachip network. This paper proposes two techniques to break through the simple static TDMA-based vertical buses while maintaining a simple communication interface. The first technique is headfirst sliding (HS) routing to reduce the waiting time for acquiring the communication time-slot. HS routing selects the best vertical bus based on the current time, taking advantage of static TDMA. The second technique extends carrier sense multiple access with collision detection (CSMA/CD) for vertical broadcast buses. We introduce a packet collision detection technique for inductive-coupling buses and propose two retransmission strategies to reduce the waiting time for packet retransmissions caused by collisions. Network simulation results show that HS routing reduces the communication latency by 39.1% compared with the conventional static TDMA bus-based 3-D NoC that uses the shortest path routing. The proposed CSMA/CD bus also improves the latency by 52.5% and throughput by 34.1%. The full-system simulation results show that HS routing and the proposed CSMA/CD technique reduce the application execution time accordingly while maintaining the average flit transfer energy overhead modest. [ABSTRACT FROM AUTHOR]

A blind source separation (BSS) is proposed to reject the crosstalk between inductive-coupling channels in 3-D systems. The phase and permutation ambiguities inherent to BSS are compensated for in the proposed technique. A continuous-time natural gradient BSS with integrator output swing bounding, which is amenable for high-speed implementation, is also proposed. Techniques to reduce the implementation complexity for a large channel array are presented. The proposed technique shows substantial improvement results for crosstalk rejection in a high-crosstalk-coupling environment. In addition, for a 3 \times 3 array channel with 1 Gb/s/channel, with a crosstalk-to-signal ratio of -3 dB, a bit-error rate of 10^-11 is obtained compared to 10^-4 without BSS. [ABSTRACT FROM PUBLISHER]

In this paper, we describe a noncontact inductive-coupling data transmission link employing rotary data encoding. A system using this data-transmission link is inherently insensitive to jitter introduced in the channel and consumes approximately 50% less power than previously reported solutions. The system is targeted for applications benefiting from simultaneous noncontact power and data transmission, such as wafer-level testing, memory card interfaces, and inter-strata data communication in 3-D integrated circuits. Functionality of the proposed link is verified experimentally with a test chip developed in an 0.18-\mu \m CMOS process. In the second part of this paper, we introduce a design of a high-speed data transceiver using rotary coding. We demonstrate that, because of properties of the rotary coding, a simple transceiver without a PLL-based CDR circuit can operate at data rates limited only by characteristics of the physical channel. For performance optimization, we have developed a new family of ternary logic gates including latches, D-flip-flops, and multiplexers. [ABSTRACT FROM PUBLISHER]

This paper presents SD-card-size wireless power transfer system for large-volume contactless memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the dc–dc converter or charge-pump circuit for data write operation into the flash memory chip. The proposed approach reduces the number of components and BOM cost and improves the total power efficiency. A vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18-\mum-CMOS with high voltage option. Voltage boost from 3.3 to 16.3 V and 1-W power transfer with 50% total efficiency have been successfully demonstrated, and the response time for the power control loop is shorter than 35 \mu\s. [ABSTRACT FROM PUBLISHER]

An inductive power and data transmission link for a noncontact memory card interface is reported. Nested clover coils improve signal-to-interference ratio and enable simultaneous power and data transmission. This capability is then used in the design of a closed-loop feedback system for improving power transfer efficiency. Interference cancellation mechanism is analyzed with both 3-D EM simulations and a newly developed compact model of coupled inductors. Performance of the proposed solutions was confirmed experimentally using a scaled-down stacked-chip prototype fabricated in a 65-nm CMOS process. Maximum data transmission rate is 6 Gb/s and the total power transfer efficiency is 5.2%–10.2% over a load resistance range of 0.1–2 k\Omega. [ABSTRACT FROM AUTHOR]

This paper presents a 30 Gb/s/link 2.2 Tb/s/mm^2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, the proposed technique doubles the operation speed and increases the data rate to 30 Gb/s/link. As a result, the data rate per layout area is increased to 2.2 Tb/s/mm^2, which is 2X that of the state-of-the-art inductive-coupling link, and 22X that of the state-of-the-art wired link. [ABSTRACT FROM PUBLISHER]

This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2~V. A data rate of 1.1 Gb/s and a clock rate of 3.3 GHz, both with an error rate <10^-12, are achieved at 0.55 V and 0.7 V supply voltage, respectively. [ABSTRACT FROM AUTHOR]