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In this brief, we present a compact model of nanoscale ferroelectric (FE) capacitors. We first use the phase-field simulation to study the polarization switching of very small FE capacitor that contains only a few grains. We show that at higher applied voltage, the entire grain undergoes a single-domain-like switching, but at lower applied voltage, the domain wall growth mechanism dominates due to the difference between the domain wall energies of bulk and defect nuclei. To create a compact model that includes this voltage dependence, we use a time-dependent domain switching model for each discrete grain with empirical modifications capturing the two different switching mechanisms. In addition, a voltage-dependent dielectric model is included to represent the nonlinear capacitance of the FE capacitor. We verify this compact model by fitting the results of phase-field modeling results with excellent agreement. [ABSTRACT FROM AUTHOR]

A new deep learning (DL)-based parameter extraction method is presented in this brief; 50k training cases are generated by Monte Carlo simulations of these preselected parameters in Berkeley short-channel IGFET model (BSIM)-common multigate (CMG). DL models are trained using backward propagation with ${C} _{\text {gg}} - {V} _{g}$ and ${I} _{d} - {V} _{g}$ as the input and selected BSIM-CMG parameters as the output. A TCAD simulated FinFET device, calibrated to Intel 10-nm node, is used to test the DL models. The DL-based parameters extraction results show an excellent fit to capacitance and drain current data, with 0.16% rms error in ${C} _{\text {gg}} - {V} _{g}$ and 6.1% rms error in ${I} _{d} - {V} _{g}$ (0.69% rms error in above-threshold-voltage ${I} _{d} - {V} _{g}$), respectively. In addition, devices with a 10% variation in gate length and oxide thickness are successfully modeled with the trained DL model. The results show tremendous promise in using the DL-based models for parameter extraction. [ABSTRACT FROM AUTHOR]

In this letter, we present a compact model of ferroelectric field-effect-transistor (FEFET). The model consists of a ferroelectric (FE) capacitor model and a Berkeley Short-channel IGFET Model (BSIM), a standard SPICE MOSFET model. The FE model, similar to the nucleation-limited-switching model, is based on the statistical multidomain dynamics of FE materials. The charge equality between FE and MOSFET is satisfied through the SPICE simulator. The model reproduces the steep switching in the reverse bias region observed in experimental FEFETs and the current drop at both major loop and minor loop switching. A versatile inverted-memory-window (IMW) model can model the IMW behavior of FEFET that may be caused by charge trapping. We demonstrate that the reported model can accurately fit the published data of Fin-FEFET and FDSOI-FEFET under different bias conditions. [ABSTRACT FROM AUTHOR]

In this work, we propose using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET current-voltage model. The benefits of having some physics-driven features in the model are discussed. Using a portion of the Berkeley Short-channel IGFET Common-Multi-Gate (BSIM-CMG), the industry-standard FinFET and GAAFET compact model, as the physics model and a 3-layer neural network with 6 neurons per layer, the resultant model can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3%, 4.1%, and 2.9%, respectively. Implications for circuit simulation are also discussed. [ABSTRACT FROM AUTHOR]

In this article, we present a compact model of metal–ferroelectric (FE)–insulator–semiconductor (MFIS) tunnel junction. Unlike the metal–FE–metal (MFM) structure with only one insulator layer, MFIS–FE tunnel junction (FTJ) contains two insulator layers and a semiconductor electrode. The complex structure makes it difficult to self-consistently solve the Poisson and charge equations. We report the first compact model of MFIS-FTJ to our knowledge. Previous modeling studies focused on numerical simulation, which is time-consuming and not applicable to circuit simulation. The presented compact model is suitable for commercial SPICE IC simulation. It includes a FE model that can capture polarization switching under arbitrary applied voltage, an insulator–semiconductor model that calculates the potential profile of the MFIS stack, and an analytical tunneling current model. We demonstrate that this model can be used to simulate and fit both n-type and p-type MFIS-FTJs. [ABSTRACT FROM AUTHOR]

We present a compact model of polycrystalline ferroelectric (FE) capacitors. The polycrystalline thin-film material is modeled as a collection of independent grains or grain groups. Each grain or grain group is characterized by its local field-dependent switching rate, which is characterized by a distribution function such as Gaussian or type-2 generalized beta distribution. This computationally efficient model accurately reproduces the published experimental polarization switching waveforms and the switching current waveforms in response to all reported applied voltage waveforms. The model tracks the polarization history so that it can simulate the transition between major and minor and among minor loops as well as accumulative polarization which cannot be captured by the conventional models. This model is intended for simulating circuits containing FE capacitors using commercial SPICE simulators for arbitrary applied voltage waveforms. It also has the capability of simulating the discrete switching and device variability in small-area FE capacitors having a small number of grains, although there is no available experimental data to check the model accuracy in this regard. [ABSTRACT FROM AUTHOR]

In this paper, we develop a compact model of antiferroelectric (AFE) capacitors. AFE material, similar to the ferroelectric (FE) material, is a good candidate for non-volatile memory applications. Unlike FE materials, there are no good compact models that can describe the AFE materials for circuit simulation. In this study, we consider the AFE material as a collection of multiple crystal groups. For each group, the polarization may switch from zero to positive or negative polarization and vice versa depending on the electric field polarity. This switching is modeled by a local field-dependent switching rate, which has a statistical distribution among the groups. We implement this model in Verilog-A and run it on a commercial SPICE simulator to demonstrate this model’s capability to reproduce the published experimental data of the dependency of the AFE capacitor switching on the writing pulse width and voltage and the major and minor loops behavior are demonstrated. [ABSTRACT FROM AUTHOR]

Drain-extended MOSFET (DEMOS) with halo implant induced laterally asymmetric channel doping shows anomalous characteristics across bias and temperature that cannot be captured by existing models. The transconductance (gm) maxima in the linear region is found to be not only a function of the peak mobility but also the halo doping density. In the saturation region, the gm characteristics show a nonmonotonic “hump” induced by the halo-region/channel-region junction barrier. Another key care-about for analog design - the drain current (ID) mismatch, also exhibits unique characteristics with excess mismatch in the weak-inversion (WI) region, in particular at low temperature. In addition, the anomalous flicker noise (1/ƒ noise) trends in the presence of high-trap density in the halo region of halo-implanted DEMOS are also discussed. In this work, we propose an analytical model based on the equivalent conductance and impedance field theory to capture these effects. The proposed model is in good agreement with measurements and numerical device simulations using technology computer-aided design (TCAD) of DEMOS across a different oxide thickness, geometry, bias, and temperature. [ABSTRACT FROM AUTHOR]

In this article, we will analyze and provide new insights into the polarization gradient effect of a ferroelectric using TCAD simulation and demonstrate how to model the polarization gradient effect using the negative capacitance FET (NCFET) compact model based on the BSIM framework. A larger value of g (the coefficient of polarization gradient effect) results in improved subthreshold slope, smaller OFF-current, smaller drain-induced barrier lowering (DIBL), and smaller output conductance. Inclusion of the polarization gradient effect in the NCFET compact model improves usability because it accurately captures the effects of negative DIBL and negative output conductance. [ABSTRACT FROM AUTHOR]

We propose an updated compact model for mobility in Nanosheet FETs. This is necessary since Nanosheet FETs exhibit significant mobility degradation with thickness and width scaling caused by centroid shift, changing effective mass due to quantum confinement as well as various crystal orientations of the various conduction planes. The model takes all of these effects into account. It has been implemented in Verilog-A and validated with experimental data. To the best of our knowledge, this is the first compact model capturing the effect of nanosheet scaling on mobility. [ABSTRACT FROM AUTHOR]

1/ ${f}$ noise is characterized on thick and thin-gate oxide-based FinFETs for different channel lengths. The devices exhibit gate bias dependence in 1/ ${f}$ noise even in the weak-inversion region of operation which cannot be explained by the existing flicker noise model. We attribute this phenomenon to the non-uniform oxide-trap distribution in energy or space. Based on our characterization results for n- and p-channel FinFETs, we have improved the BSIM-CMG industry standard compact model for the FinFETs. The improved model is able to capture the 1/ ${f}$ noise behavior over a wide range of biases, channel lengths, fin numbers, and number of fingers. [ABSTRACT FROM AUTHOR]

In this brief, we present an improved model of bulk charge effect for both drain current (${I}_{\text {DS}}$) and capacitances and its implementation in the industry standard Berkeley short-channel IGFET model (BSIM)-BULK model. The proposed model captures all the well-known and important bulk charge effects, as the Abulk term does for BSIM3/BSIM4. The model is validated with the experimental and technology computer-aided design (TCAD) data. The proposed model enhances the fitting accuracy for ${I}_{\text {DS}}$ , and more importantly its derivatives and capacitances too. [ABSTRACT FROM AUTHOR]

We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model. [ABSTRACT FROM AUTHOR]

We present a compact model for source-to-drain tunneling current in sub-10-nm gate-all-around FinFET, where tunneling current becomes nonnegligible. Wentzel–Kramers–Brillouin method with a quadratic potential energy profile is used to analytically capture the dependence on biases in the tunneling probability expression and simplify the equation. The calculated tunneling probability increases with smaller effective mass and with increasing bias. We at first use the Gaussian quadrature method to integrate Landauer’s equation for tunneling current computation without further approximations. To boost simulation speed, some approximations are made. The simplified equation shows a good accuracy and has more flexibility for compact model purpose. The model is implemented into industry standard Berkeley Short-channel IGFET Model-common multi-gate model for future technology node, and is validated by the full-band atomistic quantum transport simulation data. [ABSTRACT FROM PUBLISHER]

In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases. [ABSTRACT FROM PUBLISHER]

In this paper, we report anomalous behavior of transconductance ( gm ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The gm characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the gm behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical gm behavior. The effect of oxide thickness ( T\text {ox} ) variation on gm is also studied, which demonstrates a deviation from the conventional gm behavior for halo implanted devices with thicker T\text {ox} . A computationally efficient SPICE model is proposed to model gm characteristics which shows excellent matching with the measured data. [ABSTRACT FROM PUBLISHER]

A predictive tunnel FET compact model is proposed. Gaussian quadrature method is used to overcome the challenge of integration. This provides the flexibility to use Wentzel–Kramers–Brillouin under spatially varying electric field, to incorporate effective band edge states broadening, and to evaluate the drain current by Landauer equation with consideration of electron reflection at the tunnel junction. The model not only shows good accuracy, speed, and smoothness, but is also some predictive capability so that the effects of changing material parameters on IC characteristics are well captured. The model is validated with atomistic simulation data for several materials. [ABSTRACT FROM PUBLISHER]

In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained. [ABSTRACT FROM AUTHOR]

We present a charge-based compact model for induced gate thermal noise for a fully depleted silicon-on-insulator transistor. The model uses front- and back-gate charges as well as the respective mobilities for the development of analytical expression. The model is implemented in Verilog-A and validated with experimentally calibrated TCAD simulations. The model predicts the high-frequency behavior with good accuracy while capturing the back-bias dependence. [ABSTRACT FROM AUTHOR]

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source–drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node. [ABSTRACT FROM PUBLISHER]

In this letter, we model future generation SiGe FinFETs using the industry standard compact model BSIM-CMG. BSIM-CMG is enhanced to model these aggressively scaled devices. It is found that in these narrow fin (fin width W\textrm {fin} = 12 nm) devices spacer region resistance behaves nonlinearly with drain-current. This nonlinear resistance behavior arises due to the saturation of carrier velocity in the spacer region. Accurate modeling of spacer region nonlinearity is important to predict the drain-current and the device transconductance. The developed model captures this phenomenon very well and produces excellent agreement with experimental data. [ABSTRACT FROM AUTHOR]

In this letter, a macromodel for normally-off (enhancement mode) AlGaN/GaN-based FinFET (2-DEG channel at top with two MOS like sidewall channels) is proposed. AlGaN/GaN-based FinFET devices have improved gate control on the channel due to additional sidewall gates compared with planar structures, but device characteristics exhibit strong nonlinear dependence on fin-width. The proposed model captures both 2-DEG and sidewall channel conduction as well as the fin-width dependency on device characteristics. Model shows excellent agreement with state-of-the-art experimental data. [ABSTRACT FROM AUTHOR]

• A single neural network parameter extractor for BSIM-CMG IV and CV model is developed. • A global I-V and C-V parameter extraction for a large range of gate length is achieved. • A high fitting accuracy is demonstrated on TCAD simulated data calibrated to 10 nm node. A global I-V and C-V BSIM-CMG parameter extraction methodology based on deep learning is proposed. 100 k training datasets were generated through Monte Carlo simulation varying 28 IV and CV model parameters in the industry-standard BSIM-CMG FinFET model. For each of the 100 k Monte Carlo-selected BSIM-CMG parameter dataset, the I D -V G and C GG -V G characteristics of seven Monte Carlo-selected gate lengths ranging from 14 nm to 110 nm were generated as the input to train the parameter extraction neural network. The neural network outputs for training are the 28 model parameters' values. The neural network's capability to extract BSIM-CMG model parameters that accurately fit TCAD-generated I D -V G and C GG -V G data over a range of gate lengths was demonstrated. This marks the first time a deep learning compact model parameter extraction flow, employing a single neural network for both I-V and C-V parameters and for a range of gate length, is presented. [ABSTRACT FROM AUTHOR]

• A RRAM compact model compatible with OxRAM and CBRAM. • Accurately model experimental DC and transient data of various RRAM structures. • RRAM variation and disturb effect are modeled. • Compatible with SPICE simulation and memory circuit designs. We present a versatile compact model for resistive random-access memory (RRAM) that can model different types of RRAM devices such as oxide-RRAM (OxRAM) and conducting-bridge-RRAM (CBRAM). The model unifies the switching mechanisms of these RRAMs into a single framework. We showcase the model's accuracy in reproducing published experimental device DC and transient characteristics of various RRAM structures. We also demonstrate the model's efficacy in capturing RRAM variability and conducting 1T1R circuit simulations. [ABSTRACT FROM AUTHOR]

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C – V and I – V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction. [ABSTRACT FROM AUTHOR]