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The comparator is the basic block for data converter circuits, designing modern analog and mixed-signal systems, for example, telecommunications that interface with sensing circuits. Several analog to digital converters (ADCs) require low-power, high-speed comparators through less area of chip. The spin device-based self-calibrated comparators are accustomed to design high-speed, low-offset and power ADCs. This paper presents two spin devices based on self-calibrated comparator, which is an area and power efficient compared with other comparators. Our proposed self-calibrated comparator consumes 1.3 µW power and 0.0272 fJ energy at a supply voltage of 0.75 V. The spin devices (MTJ and a Strip), SPICE compatible model-based Verilog-A language and PTM CMOS 45 nm model are used to simulate its performance, like the power and delay, and compared it with dynamic comparators.

The pre-charge sense amplifier (PCSA) offers good trade-off between reliability, efficiency and performance. The hybrid combination in PCSA gives better result due to non-volatile nature of Magnetic Tunnel Junction. In this paper, performance of proposed Sense Amplifier (SA) has been evaluated in terms of delay and power and compared with another Sense amplifier (SA). The proposed double tail sense amplifier (DTSA) consumes 11.162 µW and 0.3405 fJ energy at the supply voltage of 0.75V. This proposed comparator can operate at high frequency. The simulations is produced to investigate its process variation with help of Monte Carlo method.

Magnetic tunnel junction (MTJ) and current induced domain wall motion in magnetic strip are used as a comparator of a flash ADC. This flash ADC has good performance in terms of power consumption and area because it uses spintronic devices in conjunction with CMOS. Motion of domain-wall (DW) in magnetic strip is a promising technique to save area and power without degrading speed. This paper proposes an energy and area efficient flash ADC based on a comparator constructed using Domain wall motion in a magnetic strip and MTJ. It has less area and power consumption than other ADCs. This 5-bit Flash ADC can operate at 250MS/s with power consumption of 1.15mW. Verilog-A Compact model is used for the domain wall and MTJ and simulation has been carried out with Cadence design tools using PDK CMOS 45nm design Kit. The results are then compared with conventional ADCs.